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Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs
Abstract:
As a switching device, a SiC MOSFET operates under high-frequency and fast switching edges, facing severe reliability challenges in the dynamic mode. The degradation of electrical characteristics of SiC MOSFETs under high-voltage dynamic switching conditions is systematically investigated in this study. It is found that the threshold voltage and on-resistance exhibit initial transient degradation but they both stabilize, with changes remaining within ±5%. They show no dependence on the pulse amplitude, frequency, duty cycle, or temperature. This is attributed to the shielding effect of the P-well structure on the electric field in the channel region, which suppresses the continuous accumulation of interface charges. Additionally, the body diode voltage drop shows no significant shift, indicating that the dynamic reverse bias stress has no substantial impact on the n-drift region. However, the blocking capability can degrade and the degradation trajectory exhibits cross-coupling effects of multiple factors. The rate of degradation is positively correlated with the pulse voltage amplitude, frequency, duty cycle, and test temperature. As these stressors increase, carriers gain higher energy in the couple electro-thermal fields, leading to enhanced charge injection efficiency and trapping depth, increased interface charge accumulation, and localized electric field distortion, resulting in nonlinear degradation of the device's blocking capability. This study reveals the degradation mechanisms of SiC MOSFET under dynamic stress conditions, providing a theoretical basis for the optimization of interface engineering and dynamic operation adaptation design of high-reliability power devices.
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69-77
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May 2026
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