Paper Titles
Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs
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Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors
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Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations
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Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs
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Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening
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Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress
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Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress
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Understanding the Influence of Different Parameters on the Dynamic VSD Behaviour of SiC MOSFETs during Power Cycling Test
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Design Space Exploration of SiC Power Module Package via Surrogate Model
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Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

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Abstract:

Intrinsic gate oxide reliability of silicon carbide (SiC) power MOSFETs has improved significantly over the years. Nonetheless, to achieve a level of overall reliability comparable to Si devices, it is essential to address extrinsic defects that could introduce early life failures in the gate oxide of SiC devices. Gate screening can be performed to eliminate these early life failures; however, proper optimization of screening methodology is required to maximize the useful life of the devices while maintaining a low failure rate and avoiding potential adverse effects, such as threshold voltage instability, due to the high gate stress during screening. In this paper, we demonstrate enhanced intrinsic and extrinsic reliability of gate oxide across two distinct wafer fabrication facilities, achieved through optimized processing and screening methodologies.

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Periodical:

Key Engineering Materials (Volume 1054)

Pages:

79-84

DOI:

https://doi.org/10.4028/p-1iEOWa

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Cite this paper

Online since:

May 2026

Authors:

Ayan K. Biswas*, Callie Woods, Daniel J. Lichtenwalner, Shadi Sabri, Sei Hyung Ryu, Brett Hull, Adam Barkley, Donald A. Gajewski, Elif Balkas

Keywords:

Gate Oxide Reliability, Gate Screening, Lifetime Modeling, SiC MOSFET, Time Dependent Dielectric Breakdown (TDDB)

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