Paper Titles
Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs
p.69
Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening
p.79
Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress
p.85
Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress
p.91
Understanding the Influence of Different Parameters on the Dynamic VSD Behaviour of SiC MOSFETs during Power Cycling Test
p.99
Design Space Exploration of SiC Power Module Package via Surrogate Model
p.115
Dynamic HV-H³TRB Test on 3.3 kV SiC MOSFET Modules
p.121
Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output
p.127
Power Cycle Failure Modes of 10 kV SiC-MOSFET Power Modules with Different Wire Bond Layouts
p.135

Understanding the Influence of Different Parameters on the Dynamic VSD Behaviour of SiC MOSFETs during Power Cycling Test

Article Preview
View Pdf By email

Abstract:

An accurate junction temperature estimation is crucial for all reliability tests (e.g., power cycling tests) of power semiconductor devices, as it directly impacts the lifetime estimation. Studies on advanced silicon carbide (SiC) MOSFETs from various manufacturers indicate that conventional static temperature calibration methods can introduce significant error in virtual junction temperature determination due to the dynamic behaviour of the body diode’s voltage drop (VSD). In this study, a similar dynamic VSD behaviour was observed by switching the gate voltage without applying a load current, using only a sense current across the body diode. However, this time-dependent dynamic VSD behaviour can be completely eliminated by applying sufficiently negative voltage. Furthermore, dynamic VSD behaviour is strongly influenced by different parameters such as gate loop inductance, gate resistance, turn-on gate voltage, junction temperature and sense current. Moreover, complementary 2D TCAD simulations under experimental conditions reveal that charge trapping and de-trapping at the SiC/SiO2 interface, together with current sharing between the channel and body diode, fundamentally govern the observed transient VSD dynamics. These findings provide critical insights for an accurate temperature determination and characterization of SiC MOSFETs under dynamic gate conditions.

You have full access to the following eBook
Robustness and Reliability of SiC MOSFET Devices, SiC MOSFET Power Modules Read eBook

Info:

Periodical:

Key Engineering Materials (Volume 1054)

Pages:

99-113

DOI:

https://doi.org/10.4028/p-HQ1kov

Citation:

Cite this paper

Online since:

May 2026

Authors:

Madhu Lakshman Mysore*, Maximilian Goller, Rahul Vijaybhai Chavda, Mohamed Alaluss, Josef Lutz, Thomas Basler

Keywords:

Body Effect, Dynamic VSD, Interface Traps, Power Cycling Test, TCAD, VSD(T) Method

Export:

RIS, BibTeX

Permissions:

Creative Commons CC BY 4.0

Share:

Citation:

* - Corresponding Author

References

[1] ECPE Guideline AQG 324: Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles, 03.1/2021, ECPE Euro-pean Center for Power Electronics e.V., May. 2021.

Google Scholar

[2] Y. Zhang, et al., "A Guideline for Silicon Carbide MOSFET Thermal Characterization based on Source-Drain Voltage," in 2023 IEEE APEC, Orlando, FL, USA, 2023, p.378–385.

DOI: 10.1109/apec43580.2023.10131449

Google Scholar

[3] J. A. O. González and O. Alatise, "A Novel Non-In-trusive Technique for BTI Characterization in SiC MOSFETs," IEEE Trans. Power Electron., vol. 34, no. 6, p.5737–5747, 2019.

DOI: 10.1109/tpel.2018.2870067

Google Scholar

[4] T. Funaki and S. Fukunaga, "Difficulties in characterizing transient thermal resistance of SiC MOSFETs," in Proc. 22nd THERMINIC. IEEE, 2016, pp.141-146.

DOI: 10.1109/therminic.2016.7749042

Google Scholar

[5] J. Breuer, et al., "Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling – a Dynamic Approach," in 2024 CIPS conference, Düsseldorf, Germany, 2024.

Google Scholar

[6] P. Fiorenza, et al., "Identification of two trapping mechanisms responsible of the threshold voltage variation in SiO2/4H-SiC MOSFETs" in Appl. Phys. Lett. 117, 103502, Sep. 2020.

DOI: 10.1063/5.0012399

Google Scholar

[7] T. Hatakeyama, et al., "Characterization of traps in SiC/SiO2 interfaces close to the conduction band by deep-level transient spectroscopy," in Jpn. J. Appl. Phys. 54 111301, 2015.

DOI: 10.7567/jjap.54.111301

Google Scholar

[8] M. Waltl, et al., "Physical Modelling of Charge Trapping Effects in SiC MOSFETs," in Materials Science Forum, ISSSN: 1662-9752, vol.1090, 2023, pp.185-191.

DOI: 10.4028/p-o083cb

Google Scholar

[9] E. Pippel, et al., "Interfaces between 4H-SiC and : Microstructure, nanochemistry, and near-interface traps," in J. Appl. Phys. 97, 034302, 2005.

DOI: 10.1063/1.1836004

Google Scholar

[10] P. Fiorenza, et al., " Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis" in Nanotechnology 29 395702, 2018.

DOI: 10.1088/1361-6528/aad129

Google Scholar

[11] TCAD Sentaurus Manual, Synopsys Inc., Mountain View, CA, USA, 2022.

Google Scholar

[12] T. Aichinger, et. al., "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs" Microelectronics Reliability, vol 80, pp.68-78, 2018.

DOI: 10.1016/j.microrel.2017.11.020

Google Scholar