Paper Titles
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Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress
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Understanding the Influence of Different Parameters on the Dynamic VSD Behaviour of SiC MOSFETs during Power Cycling Test
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Dynamic HV-H³TRB Test on 3.3 kV SiC MOSFET Modules
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Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output
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Power Cycle Failure Modes of 10 kV SiC-MOSFET Power Modules with Different Wire Bond Layouts
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Low-Inductance Packaging Design for SiC Power MOSFET Modules
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Power Cycle Failure Modes of 10 kV SiC-MOSFET Power Modules with Different Wire Bond Layouts

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Abstract:

10 kVSiC-MOSFETpowermodulesarebeingdevelopedformedium-voltageapplications, but their reliability has not yet been fully verified. This study demonstrates the power cycle test (PCT) on 10 kV SiC-MOSFET power modules with different wire bond layout designs to investigate the influence on their failure points. The 10 kV SiC-MOSFET is 8.1 mm square in size and 20 A/die. Only four source wire bonds are needed, which provides enough flexibility for the wire bond layout. The wire bonds are placed on the edge of each source pad to reduce the wire heating ∆Twire by 6.2% compared to the conventional central wire bond placement from the 3D simulation. These differences were verified in the PCT on ∆Tdiemax : 104−108 °C. As a result, itwas observed that samples with the modified layout, which achieved a lower ∆Twire, exhibited a shift in failure mode from wire lift-off to solder failure, while maintaining a similar lifetime under higher die temperatures.

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Periodical:

Key Engineering Materials (Volume 1054)

Pages:

135-142

DOI:

https://doi.org/10.4028/p-BE7jb4

Citation:

Cite this paper

Online since:

May 2026

Authors:

Masaki Takahashi*, Zhong Chao Sun, Stig Munk-Nielsen, Asger Bjørn Jørgensen

Keywords:

10 kV SiC-MOSFET, Power Cycle Failure Mode, Wire Bond Layout

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Creative Commons CC BY 4.0

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* - Corresponding Author

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