Paper Titles
Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening
p.79
Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress
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Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress
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Understanding the Influence of Different Parameters on the Dynamic VSD Behaviour of SiC MOSFETs during Power Cycling Test
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Design Space Exploration of SiC Power Module Package via Surrogate Model
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Dynamic HV-H³TRB Test on 3.3 kV SiC MOSFET Modules
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Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output
p.127
Power Cycle Failure Modes of 10 kV SiC-MOSFET Power Modules with Different Wire Bond Layouts
p.135
Low-Inductance Packaging Design for SiC Power MOSFET Modules
p.143

Low-Inductance Packaging Design for SiC Power MOSFET Modules

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Abstract:

With the continuous advancement of SiC device design and manufacturing processes, devices of the same ratings are achieving higher turn-on speeds and smaller chip areas. These improvements enhance the speed and power density of power electronic systems but also pose greater challenges for thermal management and the parasitic parameters of packaging. To address these issues, this paper proposes a multi-chip SiC power module packaging structure based on a multilayer ceramic substrate. Compared to a conventional single-layer DBC substrate, the multilayer substrate structure incorporates an additional intermediate copper layer, which serves as a current return path. Due to the close proximity between this return path and the upper copper layer, the overall loop area is reduced, thereby lowering the parasitic loop inductance. Simulation results show that the designed 800 V, 50 kW SiC power module achieves a parasitic loop inductance of around 3.22 nH at 10 MHz. In addition, traditional multilayer DBC structures are typically formed by soldering two separate DBC substrates together. Such soldered interfaces are often mechanically unstable, and electrical continuity between the upper and intermediate copper layers is not established. The structure proposed in this work adopts a monolithic substrate, in which a single 300 μm thick copper layer is embedded without the use of additional solder. Compared to conventional multilayer substrates, this configuration offers improved thermal conduction by eliminating solder interfaces and enhancing heat flow.

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Periodical:

Key Engineering Materials (Volume 1054)

Pages:

143-148

DOI:

https://doi.org/10.4028/p-KunI9m

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Cite this paper

Online since:

May 2026

Authors:

Zhao Bo Zhang, Renze Yu, Saeed Jahdi*, Olayiwola Alatise, Francesco Iannuzzo, Bernard Stark

Keywords:

Energy Density, Packaging, Power Module, SiC MOSFET

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Creative Commons CC BY 4.0

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* - Corresponding Author

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