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Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

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Abstract:

This study investigated the reliability challenges of SiC MOSFETs under continuous dual-bias stress conditions in electric vehicle (EV) applications. Accelerated dual-bias time-dependent dielectric breakdown (DB-TDDB) tests were performed on 1.2kV SiC MOSFETs by applying a negative gate-source voltage and a high drain-source voltage simultaneously. Experimental analysis and TCAD simulations revealed a nonlinear coupling effect between gate and drain biases, leading to a spatial relocation of the maximum gate oxide electric field under dual-bias conditions. An improved dual-acceleration-factor E-model was proposed to characterize this behavior. Based on this model, the projected lifetime at 1 ppm failure rate is 5.11×10¹³ hours, exceeding the 20-year automotive standard (AEC-Q101) by several orders of magnitude. Furthermore, failure analysis identified edge-thinning and JFET-region effects as two primary degradation mechanisms affecting gate oxide reliability, and corresponding process and design optimizations are proposed to mitigate this vulnerability. The findings offer critical insights for improving the reliability of SiC MOSFETs in EV applications under prolonged dual-bias stress.

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Periodical:

Key Engineering Materials (Volume 1054)

Pages:

31-37

DOI:

https://doi.org/10.4028/p-zj4Y9l

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Cite this paper

Online since:

May 2026

Authors:

Ji Hong Zhu*, Jing Jing Cui, Jin Ying Yu, Bao Hu, Ming Jiang, Bao Cheng Yuan

Keywords:

Dual-Acceleration-Factor E-Model, Dual-Bias, Edge-Thinning, Lifetime Prediction, SiC MOSFET

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Creative Commons CC BY 4.0

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* - Corresponding Author

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