Key Engineering Materials Vol. 1054

Abstract: Intrinsic gate oxide reliability of silicon carbide (SiC) power MOSFETs has improved significantly over the years. Nonetheless, to achieve a level of overall reliability comparable to Si devices, it is essential to address extrinsic defects that could introduce early life failures in the gate oxide of SiC devices. Gate screening can be performed to eliminate these early life failures; however, proper optimization of screening methodology is required to maximize the useful life of the devices while maintaining a low failure rate and avoiding potential adverse effects, such as threshold voltage instability, due to the high gate stress during screening. In this paper, we demonstrate enhanced intrinsic and extrinsic reliability of gate oxide across two distinct wafer fabrication facilities, achieved through optimized processing and screening methodologies.

Abstract: In this work, we report the impact of combined surge current stress and bipolar gate switching stress (GSS) on the threshold voltage (V_th) shift of planar SiC MOSFETs. The V_th shift exhibits a strong dependence on the sequence of these two applied stresses. It is found that both the surge current stress and GSS can separately result in a positive shift in V_th, and the V_th shift is cumulatively aggravated in the combined stresses only if the bipolar GSS is applied first. This is attributed to the generation of new defects during the bipolar gate switching, which act as trap centers for subsequent surge stress. This finding reveals the cumulative damage characteristics of SiC MOSFETs under complex operating conditions.

Abstract: This study investigates the degradation behavior of 1200 V 4H-SiC planar MOSFETs under negative high-temperature gate bias (HTGB) stress. The devices were stressed at −20 V and 150 °C for 1008 hours. Key electrical parameters, including threshold voltage (V_th) and reverse transfer capacitance (C_rss), were monitored to evaluate time-dependent changes. The results reveal a clear two-phase degradation behavior characterized by a transition between electron-dominated and hole-dominated charge injection mechanisms. In the early stage, electron injection via Fowler–Nordheim (FN) tunneling causes a positive shift in V_th and a reduction in C_rss. With prolonged stress, partial charge compensation leads to a reversal of the electrical trends. These results demonstrate a time-dependent transition between electron injection and hole injection mechanisms. The findings provide insight into the long-term reliability of planar SiC MOSFETs under negative HTGB stress.

Abstract: An accurate junction temperature estimation is crucial for all reliability tests (e.g., power cycling tests) of power semiconductor devices, as it directly impacts the lifetime estimation. Studies on advanced silicon carbide (SiC) MOSFETs from various manufacturers indicate that conventional static temperature calibration methods can introduce significant error in virtual junction temperature determination due to the dynamic behaviour of the body diode’s voltage drop (V_SD). In this study, a similar dynamic V_SD behaviour was observed by switching the gate voltage without applying a load current, using only a sense current across the body diode. However, this time-dependent dynamic V_SD behaviour can be completely eliminated by applying sufficiently negative voltage. Furthermore, dynamic V_SD behaviour is strongly influenced by different parameters such as gate loop inductance, gate resistance, turn-on gate voltage, junction temperature and sense current. Moreover, complementary 2D TCAD simulations under experimental conditions reveal that charge trapping and de-trapping at the SiC/SiO₂ interface, together with current sharing between the channel and body diode, fundamentally govern the observed transient V_SD dynamics. These findings provide critical insights for an accurate temperature determination and characterization of SiC MOSFETs under dynamic gate conditions.

Abstract: This study introduces a surrogate model-based optimization methodology to explore a wide design space of power module packages for achieving user-defined electromagnetic design objectives, such as minimizing commutation loop stray inductance, gate loop stray inductance and balancing mutual inductance. A half-bridge module with four parallel SiC devices per switch position is analyzed, incorporating 17 design variables across terminals and substrate dimensions. Using Sobol sampling, 4096 design variations were simulated in Ansys Q3D to train the surrogate model, enabling efficient gradient-based single- and multi-objective optimization. Results show that the proposed methodology significantly accelerates exploration in a wide design space and outperforms traditional expert-driven methods by identifying superior electromagnetic performance.

Abstract: In standard environmental reliability tests, Silicon Carbide (SiC) MOSFETs show a superior performance compared to their Silicon counterparts. This raises the question if the SiC modules are robust and reliable under all circumstances in the field and against all failure mechanisms or only in the standard laboratory tests. The HV-H³TRB (High Voltage – High Humidity High Temperature Reverse Bias) test is the standard test for humidity reliability and SiC modules survive this test for several thousand hours, easily surpassing the 1,000 h qualification requirement. However, in field service the devices are exposed to steep voltage slopes (high dv/dt) instead of the DC voltage stress applied in a standard HV-H³TRB. In this work, a dynamic HV-H³TRB test was performed on 3.3 kV SiC MOSFET modules for more than 4,000 h with switched high voltages of 80% V_nom, only observing minor degradations and reversible blocking capabilities.

Abstract: Paralleling SiC MOSFETs in high-power modules introduces overvoltage and oscillation risks due to parasitic capacitances and inductances. This study presents a 200 kW EV inverter module co-designed at the device and packaging level to ensure switching reliability under harsh automotive conditions. At 800 V, the planar SiC MOSFET maintained stable gate voltage, while a benchmark trench device module experienced severe ringing and failure. Kelvin-source structures and internal gate resistors mitigated parasitic turn-on, and device-level optimizations—including a 0.5 µm foundry technology, silicide gate, and hexagonal cell layout—improved body-diode performance, together with the channel mobility, blocking voltage, and minimized on-resistance and switching losses. The resulting AEPR25B12C1STJN module demonstrated effective resonance damping, matched the performance of commercial trench module FS03MR12A6MA1B in static and dynamic tests, and achieved 98% AC efficiency with over 200 kW output at 150 °C junction temperature.

Abstract: 10 kVSiC-MOSFETpowermodulesarebeingdevelopedformedium-voltageapplications, but their reliability has not yet been fully verified. This study demonstrates the power cycle test (PCT) on 10 kV SiC-MOSFET power modules with different wire bond layout designs to investigate the influence on their failure points. The 10 kV SiC-MOSFET is 8.1 mm square in size and 20 A/die. Only four source wire bonds are needed, which provides enough flexibility for the wire bond layout. The wire bonds are placed on the edge of each source pad to reduce the wire heating ∆T_wire by 6.2% compared to the conventional central wire bond placement from the 3D simulation. These differences were verified in the PCT on ∆T_diemax : 104−108 °C. As a result, itwas observed that samples with the modified layout, which achieved a lower ∆T_wire, exhibited a shift in failure mode from wire lift-off to solder failure, while maintaining a similar lifetime under higher die temperatures.

Abstract: With the continuous advancement of SiC device design and manufacturing processes, devices of the same ratings are achieving higher turn-on speeds and smaller chip areas. These improvements enhance the speed and power density of power electronic systems but also pose greater challenges for thermal management and the parasitic parameters of packaging. To address these issues, this paper proposes a multi-chip SiC power module packaging structure based on a multilayer ceramic substrate. Compared to a conventional single-layer DBC substrate, the multilayer substrate structure incorporates an additional intermediate copper layer, which serves as a current return path. Due to the close proximity between this return path and the upper copper layer, the overall loop area is reduced, thereby lowering the parasitic loop inductance. Simulation results show that the designed 800 V, 50 kW SiC power module achieves a parasitic loop inductance of around 3.22 nH at 10 MHz. In addition, traditional multilayer DBC structures are typically formed by soldering two separate DBC substrates together. Such soldered interfaces are often mechanically unstable, and electrical continuity between the upper and intermediate copper layers is not established. The structure proposed in this work adopts a monolithic substrate, in which a single 300 μm thick copper layer is embedded without the use of additional solder. Compared to conventional multilayer substrates, this configuration offers improved thermal conduction by eliminating solder interfaces and enhancing heat flow.