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Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

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Abstract:

This study proposes a refilled PMOS SiC trench MOSFET (RPTMOS) design with integrated parasitic PMOS clamping transistors to mitigate single-event burnout (SEB) susceptibility. The configuration of the core epi-refill process to realize the proposed RPTMOS is also demonstrated. Through systematic TCAD simulations, we analyze the transient lattice temperature, electric field distribution, and current density dynamics under heavy-ion irradiation (LET = 19.0 MeV·cm²/mg, Drain DC Bias VD = 500 V). The optimized structure features a grounded parasitic PMOS clamp formed by the P-connect, P-bottom, and N-drift regions, which enables efficient hole extraction and suppresses electric field crowding at the gate oxide corner. Comparative simulations reveal that the proposed design reduces peak lattice temperatures and elevates the SEB withstand voltage by ~20%. Parametric studies further demonstrate that increasing the P-connect thickness (200 Å → 400 Å) significantly enhance radiation hardness, proves the pivotal contribution from the parasitic PMOS. The findings offering a viable pathway for radiation-hardened SiC power devices in aerospace and high-energy applications.

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Periodical:

Key Engineering Materials (Volume 1055)

Pages:

75-83

DOI:

https://doi.org/10.4028/p-e0IRdP

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Cite this paper

Online since:

May 2026

Authors:

Hai Zhao Zhi*, Si Rui Feng, Xiao Ping Wang, Xin Peng Lin, Yi Tian Jiang, Hao Lin Hu, Yu Xi Wan

Keywords:

Clamped PMOS, SiC Trench MOSFET, Single Event Burn-Out, Trench Refill

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Creative Commons CC BY 4.0

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* - Corresponding Author

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