Paper Titles
Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures
p.29
Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration
p.37
Characteristics of High Current 4H-SiC Schottky Barrier Diodes
p.45
Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation
p.51
Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity
p.57
JTE-Based Termination Design and Technology Considerations for 1500 V 4H-SiC Superjunction MOSFETs
p.63
2x Current Boosting Scheme in 3300 v 4H-SiC VDMOSFET
p.69
Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET
p.75
Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications
p.85

Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Article Preview
View Pdf By email

Abstract:

In high-voltage class SiC devices, maintaining sufficient robustness against humidity and fabrication processes has become a major concern when minimizing the edge termination size. Previous research has shown that suppressing the maximum electric field on the SiC surface in the termination region improves durability in HV-H3TRB tests for 3.3 kV SBDs. In this study, we investigated the impact of the FLR design on the electric field distribution in the termination region. Simulation results showed that the termination length can be reduced without changing the maximum electric field on the SiC surface and the breakdown voltage. Furthermore, the fabricated 4.5 kV SiC SBD-embedded MOSFETs exhibited good reverse leakage characteristics, which were consistent with the simulation results.

You have full access to the following eBook
Design of SiC Power Devices Read eBook

Info:

Periodical:

Key Engineering Materials (Volume 1055)

Pages:

57-61

DOI:

https://doi.org/10.4028/p-F5Vgsj

Citation:

Cite this paper

Online since:

May 2026

Authors:

Daichi Dansako*, Tetsuya Abe, Kosuke Miyazaki, Toshikazu Tanioka, Yasuhiro Kagawa, Tetsuya Nitta

Keywords:

Edge Termination, Field Limiting Rings (FLRs), HV-H3TRB, SBD Embedded MOSFET

Export:

RIS, BibTeX

Permissions:

Creative Commons CC BY 4.0

Share:

Citation:

* - Corresponding Author

References

[1] Information on http://www.mitsubishielectric.com/news/2013/1225.html.

Google Scholar

[2] A. Q. Huang, Power Semiconductor Devices for Smart Grid and Renewable Energy Systems, Proceedings of the IEEE. 105 (2017) 2019–2047.

Google Scholar

[3] S. Sen, J. Tong, Z, Guo and A. Q. Huang, A Bottom Charge-Modulated Field Limiting Rings Termination With N-P-N Sandwich Epitaxial Wafers for 4H-SiC Devices, in Proc. APEC 2022, 957-961.

DOI: 10.1109/led.2025.3581587

Google Scholar

[4] K. Ebihara, K. Kawahara, S. Hino, K. Sadamatsu, A. Nagae, Y. Nakao, H. Watanabe and S. Yamakawa, Investigation of the Robust Edge Termination Applied to 6.5kV SiC MOSFET, Materials Science Forum, 924 (2018) 778-781.

DOI: 10.4028/www.scientific.net/msf.924.778

Google Scholar

[5] J. Zhang, H.Luo, H.Wu, Z. Wang, B. Zheng and X. Chen, Design and optimization of cell and field limiting ring termination for 1200 V 4H-SiC Junction Barrier Schottky (JBS) Diodes, in Proc. ICEPT 2022, 1-5.

DOI: 10.1109/icept56209.2022.9873379

Google Scholar

[6] K. Ebihara, H. Niwa, T. Murakami, K. Fujiyoshi, Y. Nakata, S. Okimoto, K. Hatori and K. Nishikawa. Durable Edge Termination Design of SiC SBD against Humidity, in Proc. ISPSD 2024, p.510– 513.

DOI: 10.1109/ispsd59661.2024.10579666

Google Scholar