Key Engineering Materials Vol. 1055

Abstract: Silicon carbide (SiC) has emerged as a leading material for high-power applications. However, the high density of interface states (D_it) at the SiO₂/SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4H-SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based D_it extraction algorithm. The results demonstrate that NO PDA effectively reduces D_it not only near the conduction band edge but also towards the valence band, yielding improved channel mobility (µ_FE) and enhanced threshold voltage stability.

Abstract: With ever-increasing power conversion densities in electric power converters, the volume of the converter must shrink for a certain power rating, which in turn demands the reduction in size of the energy-storing passive component. Constant power rating of those systems and the reduction of size of passive components leads to a higher switching frequency of the semiconductor power switches. At high switching frequencies, dynamic losses in the power semiconductor device dominate the overall power losses. Consequently, novel device concepts that address dynamic power losses may be superior to conventional power devices, even though they might have a higher static on-state loss. In this paper, the concept of the power tunneling field-effect transistor (Power-TFET) employing tunneling between a highly p-type doped source region and a n-type accumulation channel is proposed and compared to an equivalent LDMOS in terms of static and dynamic losses. Devices fabricated in a 2 µm 4H-SiC technology are measured and compared to evaluate the viability of the Power-TFET device concept. The fabricated Power-TFET shows high-voltage blocking capability and has a switchable tunneling junction with on-and off-state, despite showing high on-state resistance due to the tunneling through the wide bandgap of 4H-SiC. The alternative of tunneling through a switchable Schottky barrier is simulatively explored to solve the high on-state resistance of the pn-junction based Power-TFET.

Abstract: We have introduced a new 1200V 4H-SiC MOSFET as Wolfspeed's Gen4 MOSFET, which offers compatible Rds,on, improved dynamic switching energy losses, reduced Qrr, and enhanced short circuit withstand time performance. In this study, we examine the P-body effect resulting from multi-step ion implantation and its significant impact on both the static and dynamic characteristics of SiC MOSFETs, specifically focusing on body-diode reverse recovery, short circuit withstand time (Tscwt), and observed switching energy losses in the 1.2 kV 4H-SiC power MOSFETs within this Gen4 series. Our findings are expected to contribute valuable insights into optimizing the design and operation of SiC MOSFETs, ultimately supporting the needs of modern power electronic systems that demand greater performance and efficiency.

Abstract: This paper reports on the comparative analysis of several 6.5 kV-rated 4H-SiC Junction Barrier Schottky integrated MOSFETs (JBSFETs) and 4H-SiC MOSFET to assess their forward conduction, 3^rd quadrant behavior, and blocking characteristics. Among different JBSFET architectures, the Island P+ JBSFET achieved nearly identical specific on-resistance (R_on,sp) to the nominal MOSFET while delivering superior 3^rd quadrant conduction and maintaining a high breakdown voltage. Further optimization of Schottky width demonstrated a trade-off between leakage suppression and 3^rd quadrant conduction efficiency that underscores the Island P+ JBSFET’s potential as a reliable high-voltage SiC power device for next-generation applications.

Abstract: We have demonstrated an integrated 3.3 kV 4H-SiC vertical planar bidirectional (BD) conventional (Conv) power DMOSFET in common-drain (CD) configuration using two commercially available power DMOSFET dies and study its operation down to 77 K (-196 °C) to evaluate its cryogenic static and switching performance. The BD conduction and blocking are achieved down to 77 K. The measured specific on-resistance (R_ON,sp) of the BD MOSFET at room temperature (RT) is 26 mΩ-cm², approximately twice that of the unidirectional device. It increases by 54% when cooled to 77 K due to a substantial increase in channel and possibly JFET on-resistance components. In addition, the extracted specific switching losses (E_ON,sp and E_OFF,sp) increases by 33% (13%) at 195K (–77 °C) and by 83% (88%) at 77 K, relative to their RT values. These increases are primarily attributed to the substantial rise in R_ON,sp at 77 K. As a result, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance under cryogenic operation, driven mainly by the significant increase in channel and JFET resistance components.

Abstract: Several 1.2kV 4H-SiC Bi-Directional MOSFETs (BiD-MOS) design approaches were successfully fabricated and evaluated based on their electrical characteristics. Both monolithic integration design approaches exhibited negligible differences in conduction, blocking, and switching characteristics when compared to their 2-Chip counterpart. However, during the short-circuit withstand time testing, severe gate oscillations were observed in the 2-Chip design, which was not an issue present in either monolithic configuration. As a result of its robust electrical behavior, monolithic integration emerges as a promising design approach for developing efficient and reliable Bi-Directional Switches.

Abstract: Silicon carbide (SiC) Schottky barrier diodes (SBDs) have become critical components in power electronics due to their excellent high-voltage, high-temperature tolerance, and fast switching capability. However, increasing device area to improve current-carrying capability increases the total number of defects, which leads to an increase in reverse leakage current and reduces wafer yield. To improve current distribution uniformity within SiC module packaging, reduce system size and weight, and enhance the current-carrying capacity and high-temperature stability of a single SBD, this paper develops 750V/100A and 1200V/100A SiC SBDs on 6-inch wafers. For the 750V/100A device, the corresponding forward voltage (V_F) at forward current (I_F) of 100 A is 1.68 V. For the 1200V/100A device, the corresponding V_F is 1.75V. Calculation based on the current voltage characteristics shows that the ideal factors of 750V/100A and 1200V/100A devices are 1.01 and 1.04, respectively, which are very close to 1. It demonstrates excellent Schottky contact and a high-quality interface. The devices exhibit high-temperature stability, meeting the demands of high-temperature applications.

Abstract: This paper presents the fabrication and characterization of a cell-to-cell integrated SiC lateral bi-directional MOSFET (L-BiD-MOSFET), with blocking performance analyzed through correlation of experimental results and 3D TCAD simulations. The fabricated devices exhibit a breakdown voltage of 600 V, notably lower than the 900 V predicted by 2D simulations. To address this discrepancy, 3D TCAD simulations were performed, which identified electric field crowding at the finger edges as the dominant factor limiting the breakdown voltage. To mitigate this effect, an extended P-top edge design was introduced, which increases the simulated breakdown voltage by more than 10%. Experimental results on devices incorporating the proposed design confirm improved breakdown capability, demonstrating good agreement with simulations. These results highlight the importance of accurate 3D simulation for edge effects in lateral structures. Overall, the proposed design strategy provides valuable guidance for the development of high-performance lateral bi-directional SiC power devices.

Abstract: In high-voltage class SiC devices, maintaining sufficient robustness against humidity and fabrication processes has become a major concern when minimizing the edge termination size. Previous research has shown that suppressing the maximum electric field on the SiC surface in the termination region improves durability in HV-H³TRB tests for 3.3 kV SBDs. In this study, we investigated the impact of the FLR design on the electric field distribution in the termination region. Simulation results showed that the termination length can be reduced without changing the maximum electric field on the SiC surface and the breakdown voltage. Furthermore, the fabricated 4.5 kV SiC SBD-embedded MOSFETs exhibited good reverse leakage characteristics, which were consistent with the simulation results.