The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Article Preview

Abstract:

With ever-increasing power conversion densities in electric power converters, the volume of the converter must shrink for a certain power rating, which in turn demands the reduction in size of the energy-storing passive component. Constant power rating of those systems and the reduction of size of passive components leads to a higher switching frequency of the semiconductor power switches. At high switching frequencies, dynamic losses in the power semiconductor device dominate the overall power losses. Consequently, novel device concepts that address dynamic power losses may be superior to conventional power devices, even though they might have a higher static on-state loss. In this paper, the concept of the power tunneling field-effect transistor (Power-TFET) employing tunneling between a highly p-type doped source region and a n-type accumulation channel is proposed and compared to an equivalent LDMOS in terms of static and dynamic losses. Devices fabricated in a 2 µm 4H-SiC technology are measured and compared to evaluate the viability of the Power-TFET device concept. The fabricated Power-TFET shows high-voltage blocking capability and has a switchable tunneling junction with on-and off-state, despite showing high on-state resistance due to the tunneling through the wide bandgap of 4H-SiC. The alternative of tunneling through a switchable Schottky barrier is simulatively explored to solve the high on-state resistance of the pn-junction based Power-TFET.

You have full access to the following eBook

Info:

* - Corresponding Author

[1] G. E. Moore, "Cramming More Components Onto Integrated Circuits," Proc. IEEE, vol. 86, no. 1, p.82–85, 1998.

DOI: 10.1109/jproc.1998.658762

Google Scholar

[2] H. Ohashi, "Power electronics innovation with next generation advanced power devices," Proceedings of the 25th International Telecommunications Energy - INTELEC '03, pp.9-13, 2003. [Online]. Available: https://​ieeexplore.ieee.org​/​document/​1252084

Google Scholar

[3] J. Zou, N. C. Brooks, S. Coday, N. M. Ellis, and R. C. Pilawa-Podgurski, "On the Size and Weight of Passive Components: Scaling Trends for High-Density Power Converter Designs," in 2022 IEEE 23rd Workshop on Control and Modeling for Power Electronics (COMPEL 2022): Tel-Aviv, Israel, June 20-23, 2022, Tel Aviv, Israel, 2022, p.1–7.

DOI: 10.1109/compel53829.2022.9829957

Google Scholar

[4] T. Heckel, C. Rettner, and M. Marz, "Fundamental efficiency limits in power electronic systems," in 2015 IEEE International Telecommunications Energy Conference (INTELEC), Osaka, Japan, 2015, p.1–6.

DOI: 10.1109/intlec.2015.7572399

Google Scholar

[5] W. Hansch, C. Fink, J. Schulze, and I. Eisele, "A vertical MOS-gated Esaki tunneling transistor in silicon," Thin Solid Films, vol. 369, 1-2, p.387–389, 2000.

DOI: 10.1016/S0040-6090(00)00896-8

Google Scholar

[6] M. T. Bohr and I. A. Young, "CMOS Scaling Trends and Beyond," IEEE Micro, vol. 37, no. 6, p.20–29, 2017.

DOI: 10.1109/MM.2017.4241347

Google Scholar

[7] A. C. Seabaugh and Q. Zhang, "Low-Voltage Tunnel Transistors for Beyond CMOS Logic," Proc. IEEE, vol. 98, no. 12, p.2095–2110, 2010.

DOI: 10.1109/JPROC.2010.2070470

Google Scholar

[8] W. Vandenberghe and A. Verhulst, "Tunnel field-effect transistor with gated tunnel barrier," USA US8120115B2, Feb 21, 2012.

Google Scholar

[9] B. J. Baliga, Fundamentals of power semiconductor devices. Cham, Switzerland: Springer, 2019.

Google Scholar

[10] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ, USA: John Wiley & Sons, Inc, 2006. [Online]. Available: https://​onlinelibrary.wiley.com​/​doi/​book/​10.1002/​0470068329

Google Scholar

[11] A. May et al., "A 4H-SiC CMOS Technology enabling Smart Sensor Integration and Circuit Operation above 500 °C," in 2024 Smart Systems Integration Conference and Exhibition (SSI): 16-18 April 2024: conference location: Hamburg, Germany, Hamburg, Germany, 2024, pp.1-5.

DOI: 10.1109/ssi63222.2024.10740550

Google Scholar

[12] D. Haehnel, I. A. Fischer, A. Hornung, A.-C. Koellner, and J. Schulze, "Tuning the Ge(Sn) Tunneling FET: Influence of Drain Doping, Short Channel, and Sn Content," IEEE Trans. Electron Devices, vol. 62, no. 1, p.36–43, 2015.

DOI: 10.1109/TED.2014.2371065

Google Scholar

[13] K. K. Bhuwalka, J. Schulze, and I. Eisele, "A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET," IEEE Trans. Electron Devices, vol. 52, no. 7, p.1541–1547, 2005.

DOI: 10.1109/TED.2005.850618

Google Scholar

[14] P. G. Neudeck, J. A. Powell, A. J. Trunek, and D. J. Spry, "Step Free Surface Heteroepitaxy of 3C-SiC Layers on Patterned 4H/6H-SiC Mesas and Cantilevers," MSF, 457-460, p.169–174, 2004.

DOI: 10.4028/www.scientific.net/MSF.457-460.169

Google Scholar

[15] S. Chen et al., "High-quality heteroepitaxy of ε-Ga 2 O 3 films on 4H-SiC substrates grown via MOCVD," CrystEngComm, vol. 26, no. 25, p.3363–3369, 2024.

DOI: 10.1039/D4CE00283K

Google Scholar

[16] M. Hu et al., "Heteroepitaxy of N-polar AlN on C-face 4H-SiC: Structural and optical properties," APL Materials, vol. 11, no. 12, 2023.

DOI: 10.1063/5.0168970

Google Scholar

[17] F. Lanois, "Vertical controlled Schottky diode for use in forward type rectifier, has driver surrounded by insulator that extends in thin layer according to direction, and interdependent control electrode secured to conducting material," FR2975531 (A1), FR FR20110054215 20110516, Nov 23, 2012.

Google Scholar

[18] M. Schwarz et al., "The Schottky barrier transistor in emerging electronic devices," Nanotechnology, vol. 34, no. 35, 2023.

DOI: 10.1088/1361-6528/acd05f

Google Scholar

[19] L. Knoll and R. Minamisawa, "VERTICAL POWER SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING SUCH A DEVICE," EP3255676 (A1), EP EP20160173688 20160609, Dec 13, 2017.

Google Scholar

[20] B. J. Baliga, "The pinch rectifier: A low-forward-drop high-speed power diode," IEEE Electron Device Lett., vol. 5, no. 6, p.194–196, 1984.

DOI: 10.1109/EDL.1984.25884

Google Scholar

[21] Synopsys, Inc., "Sentaurus™ Device User Guide: Version Q-2019.12," Synopsys, Inc., Dec. 2019.

Google Scholar