Key Engineering Materials Vol. 1057

Abstract: Gated Hall measurements of lateral MOSFET devices can be used to directly measure the inversion layer free carrier density and carrier Hall mobility. From this measurement the total number of charged interface traps (N_IT) can be extracted. This provides useful insight into the degree of Coulomb scattering expected. By obtaining gated Hall data from 4° off-axis Si-face (0001) 4H-SiC MOSFETs with varied p-well doping levels, mobility limiting components can also be estimated. For these samples it is observed that interface trapped charge is almost half of the total inversion charge, and thus Coulomb scattering dominates at low Vgs or low transverse (or normal) effective field; while phonon scattering may dominate at moderate effective field, and surface roughness only limits mobility at gate fields higher than the rated usage, or at doping levels much higher than 2×10¹⁸ cm^-3.

Abstract: Visible light emission was observed for negative-bias gate stress of n-channel power MOSFETs in 4H-SiC. The emission intensity is approximately proportional to the current through the gate oxide; and its pattern follows the configuration of active MOSFET channels. We relate the emission to recombination of the electrons injected from the gate into the oxide with valence-band holes from SiC at the surface states at the SiC-to-oxide interface. The gate leakage imaging technique may be helpful for locating different types of gate oxide current crowding, which crowding might cause enhanced wear-out of the gates and early device failure.

Abstract: The far-UVC band (200–240 nm) is highly attractive for germicidal and solar-blind detection. To address limited surface carrier collection in epitaxial SiC phototransistors, we designed fully ion-implanted lateral phototransistors by combining transistor physics with CMOS-compatible processing. The lateral base width was systematically varied from 1 to 8 μm to investigate its influence on carrier transport and gain. A narrower base significantly enhanced photocurrent amplification, with the 1 μm device reaching 100.7 A/W at 200 nm and 60.0 A/W at 240 nm, while maintaining amplification up to the ~380 nm cutoff. Moreover, dark currents remained as low as 10⁻¹¹ A, confirming the advantage of structural engineering for high-performance far-UVC SiC phototransistors.

Abstract: This paper presents a comprehensive electrical evaluation of a 1.2 kV SiC vertical MOSFET incorporating a novel SiN gate dielectric. Compared to a reference device with thermally grown SiO₂, the proposed MOSFET achieves superior static performance and lower dynamic losses. Notably, the reduced losses stem from a lower gate–drain capacitance (C_GD). Furthermore, the novel MOSFET demonstrates superior thermal and electrical stability of the threshold voltage. All these findings underscore the potential of higher-k dielectrics to simultaneously optimize both static and dynamic performances in SiC power MOSFETs, paving the way for more efficient high-voltage power switches.

Abstract: SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO₂ interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Abstract: Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently can determine device lifetime. Most studies of BTI in SiC MOSFETs have characterized the threshold voltage (V_T) but not the interface trap density (N_it), leaving uncertainty about the relative contributions of carrier capture and trap creation to the V_T shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we measure N_it during positive bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in V_T and hysteresis using the triple-sense method [1], [2] for comparison with the N_it changes to evaluate whether the changes in N_it are responsible for the V_T and/or hysteresis changes, and demonstrate the utility of the technique for reliable characterization of V_T and hysteresis in SiC MOSFETs.

Abstract: In this paper, the electrical characterizations of a 4H-SiC CMOS NOT logic gate are performed in the temperature range from 300K down to 100K and the results are analyzed. The integrated circuit is fabricated with the Fraunhofer IISB 4H-SiC 2μm CMOS technology and the lateral NMOSFET and PMOSFET have channel form factor of 6/6 and 44/6, respectively. The circuit is supplied with a 20V. The curves show a reduction of the threshold voltage from 8.96V to 6.85V reducing the temperature from 300K to 100K and an ever-widening region in the High side (NMOSFET in saturation and PMOSFET in triode regime) compared to the Low side (NMOSFET in triode and PMOSFET in saturation regime). However, the noise margins are still wide enough for practical applications, making the circuit still useful. The behavior can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. Finally, analysis also focuses on the power dissipation during the transition of the output voltage from high (low) to low (high).

Abstract: Experimental analysis of 4H-SiC lateral MOSFETs characteristics up to 773K is shown. The reduction of threshold voltage, V_TH, and the increase of the field effect channel mobility, µ_CH, with temperature cause an increase of MOSFET current up to 623K. However, when scattering with lattice vibration starts to be predominant, µ_CH decreases with an abrupt drop at 773K, reducing MOSFET current. Channel resistance, R_CH, decreases with the temperature up to the range between 523 K and 573 K, implying possible thermal instability effects. However, when the temperature increases over this range, the thermal scattering predominates and R_CH again increases, ensuring thermal stability of MOSFETs.

Abstract: The repetitive peak forward surge current (I_F,RM) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the non-repetitive peak forward surge current value (I_F,SM) in datasheets, which is generally determined from derated measured peak currents that cause diode failures. Consequently, it is assumed that I_F,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine I_F,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature does not exceed the maximum device rating, which is 175°C for the commercially available devices analysed in this study.