Key Engineering Materials Vol. 1057

Abstract: This work investigates the short-circuit (SC) reliability of Split-Gate (SG) versus planar 4H-SiC MOSFETs through TCAD simulations. While SG-MOSFETs effectively reduce gate-drain capacitance and improve switching performance, SG-MOSFETs exhibit enhanced short-circuit failure effects. Structural optimization—such as thicker drift regions, extended gate lengths, and narrowed JFET widths—can improve SC withstand time (SCWT). However, SG-MOSFETs suffer from intensified electric field crowding and enhanced drain-induced barrier lowering (DIBL), leading to greater post-SC leakage and thermal instability. Results suggest SG-MOSFETs require careful field and oxide engineering to ensure reliability under fault conditions.

Abstract: This study investigates the influence of active cell geometry on the static performance of 10-kV 4H-Silicon Carbide (SiC) Junction Barrier Schottky (JBS) diodes. Two types of diodes were fabricated and characterized, one with a hexagonal cell and the other with a stripe cell. While forward conduction characteristics were comparable, the reverse leakage current of the hexagonal cell was more than two orders of magnitude lower than that of the stripe cell at 8 kV. 3D TCAD simulations revealed that this discrepancy stems from strong electric field concentrations both at the bottom corners of the P⁺ junctions and at the center of the Schottky contact in the stripe structure. These localized fields reduce the Schottky barrier height and enhance electron injection. In contrast, the hexagonal cell exhibited a more uniform electric field distribution in both regions, effectively suppressing leakage current. These findings underscore the critical role of active cell geometry in achieving robust reverse blocking performance in ultra-high-voltage SiC JBS diodes by clarifying the physical mechanisms contributing to leakage current behavior.

Abstract: We show that various commercially available silicon carbide MOSFETs exhibit significant gate leakage current at gate voltages below 20 V. With prolonged negative bias stress, this leakage current reduces by several orders of magnitude. Literature [1–3] suggests that this current is due to hole current from the silicon carbide and explain the current reduction by the discharge of electrons at the SiC/SiO₂-interface. However, measurements on n⁺-doped SiC-MOSCAPs, where we avoid hole current, exhibit similar gate leakage behavior, indicating that there might be an alternative explanation. Further measurements show that the threshold voltage is not significantly impacted by the negative gate bias stress, indicating that the channel region is not involved in the gate leakage current. Devices with a floating source do not show leakage, and we therefore conclude that the gate leakage is located in the source region. An analytical calculation is used to show that field enhancement at the edges of the polysilicon gate electrode, assuming a corner radius below 10 nm, may explain the onset voltage of the gate leakage current at negative bias. Alternatively, gate oxide damage from the polysilicon etching process, may also explain the leakage current. The reduction of the onset voltage of the gate leakage with prolonged negative voltage gate stress, may be explained by significant electron trapping due to the high local current density at the poly-silicon gate electrode corner.

Abstract: MeV-SJ-MOSFET with short tapered SJ columns was developed by high-energy (MeV) Al ion implantation and was evaluated for the reverse recovery characteristics and the body diode reliability compared to those of Multiepi-SJ. MeV-SJ alleviated the increase in on-resistance at elevated temperatures regardless of short SJ columns and exhibited soft reverse recovery characteristics due to the short tapered SJ shape. MeV-SJ also suppressed the body diode degradation more than Multiepi-SJ. It was considered that the carrier lifetime of drift layer of MeV-SJ may be decreased by non-radiative defects.

Abstract: Silicon carbide (SiC) MOSFETs are widely utilized in power device applications for their numerous advantages, and the device’s properties can be further optimized through the implementation of trench structures. The formation of the trench structure is a multi-step process, in which it is important to monitor the result of each step and ensure that the structure meets the desired requirements. OCD (optical critical dimension) metrology can provide a fast, non-destructive solution for this purpose. In this article, an OCD analysis of structures at two different process steps is presented and compared with the results from the electron microscopy images. OCD results show high sensitivity to the geometrical dimensions of the structure and produce a good correlation with the electron microscopy images. This metrology can provide a means to detect subtle structural differences without causing any damage to the sample.

Abstract: This study investigates static and dynamic behavior of a 3.3 kV semi-Superjunction (SJ) MOSFET, compared with a conventional planar MOSFET. The semi-SJ was designed using a cost-effective trench side-wall implantation and SiO₂ refill fabrication method and evaluated through TCAD simulations. The optimized semi-SJ MOSFET designs, reduces R_ON by 19% and increases BV by 500 V compared with the planar MOSFET, while maintaining a comparable reverse recovery charge (Q_RR). The proposed semi-SJ design demonstrated the best R_ON×Q_RR figure of merit (17.8 mΩ·µC), outperforming the conventional planar MOSFET design (19.7 mΩ·µC).

Abstract: We generalize a recent Si P-i-N reverse-recovery (RR) model to more accurately capture 4H-SiC diode behavior by adding deep-acceptor-limited anode injection, strong recombination (due to >100x shorter optimized high-level lifetimes compared to Si), and improved modeling of the depletion layer dynamics. Closed-form expressions for the growth of the depletion layer are derived, enabling analytical estimates for Q_RR, t_RR, and J_PR. The model is validated against Sentaurus RR simulations of optimized 4H-SiC P-i-N diodes spanning BV = 6–17kV and di/dt = 10 A/µs–10 kA/µs, achieving an average reduction in error of >90% for estimations of key switching performance parameters (Q_RR, t_RR, J_PR). By correctly capturing the dependence of Q_RR on di/dt, the model enables better estimates for the high-level lifetime (τ_HL) directly from the RR waveforms. The differential form enables straightforward utilization of the model to analyze non-idealized RR waveforms. Overall, the generalized model reveals a more favorable Q_RR–V_F trade-off than implied by the unmodified Si model and improves first-order device optimization prior to full design.

Abstract: We report an anomalous reverse-recovery (RR) of the body diode in a 3.3 kV 4H-SiC superjunction (SJ) DMOSFET: at 77 K, Q_RR,sp increases by 1.4×–3.5× versus room temperature and 5× versus 195 K, and J_PR increases by >2×, while t_RR changes by only <30ns. A clear dependence of Q_RR,sp on the ramp rate at 77K indicates the Q_RR,sp is not due to additional depletion charge. Current-controlled negative resistance (CCNR) is also observed solely for the SJ body diode at 77K. The voltage waveforms strongly suggest the additional Q_RR,sp is due to dynamic breakdown of the SJ due to transient charge imbalance of the pillars caused by delayed hole emissions of the deep acceptors. The anomalous behavior is qualitatively reproduced in simulation. We also benchmark a 3.3kV Charge Balance (CB) 4H-SiC DMOSFET along with the SJ device from 77–423 K using an inductive double-pulse test. For T > 77 K the switching for both devices is dominated by the depletion capacitance (weak Q_RR,sp dependence on the ramp rate): the SJ device turns off faster (t_RR = 0.3–0.8× CB), is snappier (t_B/t_A = 0.23–0.56× CB), and shows larger J_PR (1.8–2.8× CB) while recovering less charge (Q_RR,sp = 0.4–0.8× CB). The CB device shows the expected increase of Q_RR,sp with temperature and only modest t_RR temperature variation. Overall, the CB device provides softer, predictable RR without a cryogenic anomaly, whereas SJ delivers the shortest t_RR above 77 K but exhibits the 77 K anomalous increase and is consistently snappier.

Abstract: This paper investigates the dynamic conduction behavior of silicon carbide (SiC) MOSFETs in thesub-threshold regime. We demonstrate that controlled gate bias preconditioning, combined with timeresolvedelectrical measurements in thermal equilibrium, reveals a notable drift in the source-drainvoltage Vsd. The direction of this drift depends on the polarity of gate preconditioning and is directlyrelated to variations in the channel conduction. These effects are shown to be attributed to chargerelease from deep oxide traps, leading to a gradual shift in the flat-band voltage (Vfb) over time.Experimental results reveal that these dynamic effects are most prominent in the depletion and weakinversion regimes. Our findings highlight the influence of oxide trap dynamics on the body diodeforward voltage (Vf) and its significance for the reliability of SiC devices, specifically in its role asthe temperature-sensitive parameter.

Abstract: This study demonstrates that the output capacitance (C_oss) of a 4H-SiC MOSFET is proportional to the length of JFET (L_JFET) at a low V_ds, since under this condition, the gate-to-drain capacitance (C_gd) may account for nearly half of C_oss. Furthermore, when V_ds is low, the C_oss of MOSFETs with square and hexagonal cell topologies is approximately 20% and 25% higher than that of MOSFETs with the strip cell topology, respectively, due to larger JFET areas. However, when V_ds is higher, the C_oss of MOSFETs with square and hexagonal cell topologies is lower because of the lower drain-to-source capacitance (C_ds) resulting from smaller Pwell areas. The split-gate MOSFET can reduce C_gd, but the smaller poly-gate area decreases the depletion capability, resulting in a higher C_ds. As L_JFET of the MOSFET decreases, C_gd becomes lower, which may shorten the switching time, but due to the increased length of Pwell (L_PW), the reverse recovery current (I_rr) increases. This study proposes partially increasing the gate oxide thickness. Although this may slightly increase C_ds, the shorter switching time results in a 5% reduction in the turn-on switching loss (E_on).