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Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs
Abstract:
We show that various commercially available silicon carbide MOSFETs exhibit significant gate leakage current at gate voltages below 20 V. With prolonged negative bias stress, this leakage current reduces by several orders of magnitude. Literature [1–3] suggests that this current is due to hole current from the silicon carbide and explain the current reduction by the discharge of electrons at the SiC/SiO2-interface. However, measurements on n⁺-doped SiC-MOSCAPs, where we avoid hole current, exhibit similar gate leakage behavior, indicating that there might be an alternative explanation. Further measurements show that the threshold voltage is not significantly impacted by the negative gate bias stress, indicating that the channel region is not involved in the gate leakage current. Devices with a floating source do not show leakage, and we therefore conclude that the gate leakage is located in the source region. An analytical calculation is used to show that field enhancement at the edges of the polysilicon gate electrode, assuming a corner radius below 10 nm, may explain the onset voltage of the gate leakage current at negative bias. Alternatively, gate oxide damage from the polysilicon etching process, may also explain the leakage current. The reduction of the onset voltage of the gate leakage with prolonged negative voltage gate stress, may be explained by significant electron trapping due to the high local current density at the poly-silicon gate electrode corner.
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75-80
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May 2026
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