Paper Titles
Preface
Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements
p.1
Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress
p.7
Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors
p.13
1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric
p.19
Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and Its Relation with Transconductance
p.29
Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements
p.35
Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K
p.43
Characterization of 4H-SiC Lateral MOSFETs up to 773 K
p.49

1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

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Abstract:

This paper presents a comprehensive electrical evaluation of a 1.2 kV SiC vertical MOSFET incorporating a novel SiN gate dielectric. Compared to a reference device with thermally grown SiO2, the proposed MOSFET achieves superior static performance and lower dynamic losses. Notably, the reduced losses stem from a lower gate–drain capacitance (CGD). Furthermore, the novel MOSFET demonstrates superior thermal and electrical stability of the threshold voltage. All these findings underscore the potential of higher-k dielectrics to simultaneously optimize both static and dynamic performances in SiC power MOSFETs, paving the way for more efficient high-voltage power switches.

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Periodical:

Key Engineering Materials (Volume 1057)

Pages:

19-27

DOI:

https://doi.org/10.4028/p-6BmS4C

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Cite this paper

Online since:

May 2026

Authors:

Tommaso Stecconi*, Roger Stark, Paula Reigosa, Nick Schneider, Coris Li, Leon Liang, Lars Knoll

Keywords:

Dynamic Losses, High-K, SiN

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Creative Commons CC BY 4.0

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* - Corresponding Author

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