Paper Titles
Preface
Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements
p.1
Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress
p.7
Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors
p.13
1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric
p.19
Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and Its Relation with Transconductance
p.29
Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements
p.35
Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K
p.43
Characterization of 4H-SiC Lateral MOSFETs up to 773 K
p.49

Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

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Abstract:

Visible light emission was observed for negative-bias gate stress of n-channel power MOSFETs in 4H-SiC. The emission intensity is approximately proportional to the current through the gate oxide; and its pattern follows the configuration of active MOSFET channels. We relate the emission to recombination of the electrons injected from the gate into the oxide with valence-band holes from SiC at the surface states at the SiC-to-oxide interface. The gate leakage imaging technique may be helpful for locating different types of gate oxide current crowding, which crowding might cause enhanced wear-out of the gates and early device failure.

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Periodical:

Key Engineering Materials (Volume 1057)

Pages:

7-12

DOI:

https://doi.org/10.4028/p-h2cCpq

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Cite this paper

Online since:

May 2026

Authors:

Andrei Konstantinov, Shagufta Naureen, Sergey Reshanov, Jang Kwon Lim*

Keywords:

4H-Silicon Carbide (SiC), Gate Leakage, Gate Stress, SiC-MOSFET

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Creative Commons CC BY 4.0

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* - Corresponding Author

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