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HomeKey Engineering MaterialsKey Engineering Materials Vol. 1057Investigation of SiC MOSFETs Gate Capacitance Peak...

Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and Its Relation with Transconductance

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Abstract:

SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO₂ interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

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Performance Analysis of SiC Power Devices

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Periodical:

Key Engineering Materials (Volume 1057)

Pages:

29-34

DOI:

https://doi.org/10.4028/p-IkqQM7

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Online since:

May 2026

Authors:

Ilaria Matacena*, Luca Maresca, Alessandro Borghese, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento

Keywords:

Capacitance Measurements, Capacitance Peak, Gate Capacitance, Transconductance

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* - Corresponding Author

[1] B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

[2] C. Raynaud, et al., Comparison of trapping–detrapping properties of mobile charge in alkali contaminated metal‐oxide‐silicon carbide structures, Applied physics letters 66, no. 18: 2340-2342, (1995).

DOI: 10.1063/1.113976

[3] D. Peters et al., Investigation of threshold voltage stability of SiC MOSFETs, ISPSD, (2018).

[4] V. V. Afanasev, et al., Intrinsic SiC/SiO2 interface states, physica status solidi (a) 162, no. 1: 321-337, (1997).

DOI: 10.1002/1521-396x(199707)162:1<321::aid-pssa321>3.0.co;2-f

[5] Lancellotti, L., Lisi, N., Veneri, P. D., Bobeico, E., Matacena, I., & Guerriero, P. (2019, July). Graphene-on-Silicon solar cells with graphite contacts. In 2019 International Conference on Clean Electrical Power (ICCEP) (pp.199-203). IEEE.

DOI: 10.1109/iccep.2019.8890134

[6] Gobbo, C., Di Palma, V., Trifiletti, V., Malerba, C., Valentini, M., Matacena, I., ... & Tseberlidis, G. (2023). Effect of the ZnSnO/AZO interface on the charge extraction in Cd-free kesterite solar cells. Energies, 16(10), 4137.

DOI: 10.3390/en16104137

[7] Sonnet, A. M., Hinkle, C. L., Heh, D., Bersuker, G., & Vogel, E. M. (2010). Impact of semiconductor and interface-state capacitance on metal/high-k/GaAs capacitance–voltage characteristics. IEEE transactions on electron devices, 57(10), 2599-2606.

DOI: 10.1109/ted.2010.2059029

[8] Lancellotti, L., Bobeico, E., Della Noce, M., Veneri, P. D., & Matacena, I. (2018, June). Work function determination of transparent contact for a: Si/c-Si heterojunction solar cells. In 2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC/I&CPS Europe) (pp.1-5). IEEE.

DOI: 10.1109/eeeic.2018.8493739

[9] Matacena, I., Guerriero, P., Lancellotti, L., Alfano, B., De Maria, A., La Ferrara, V., ... & Daliento, S. (2023). Impedance spectroscopy analysis of perovskite solar cell stability. Energies, 16(13), 4951.

DOI: 10.3390/en16134951

[10] Westerhoff, U., Kurbach, K., Lienesch, F., & Kurrat, M. (2016). Analysis of lithium‐ion battery models based on electrochemical impedance spectroscopy. Energy Technology, 4(12), 1620-1630.

DOI: 10.1002/ente.201600154

[11] Matacena, I., Lancellotti, L., Daliento, S., Alfano, B., De Maria, A., La Ferrara, V., ... & Guerriero, P. (2023). Impedance Spectroscopy of Perovskite Solar Cells With SnO 2 Embedding Graphene Nanoplatelets. IEEE Journal of Photovoltaics.

DOI: 10.1109/jphotov.2023.3301674

[12] Turut, A. (2020). On current-voltage and capacitance-voltage characteristics of metal-semiconductor contacts. Turkish Journal of Physics, 44(4), 302-347.

DOI: 10.3906/fiz-2007-11

[13] Matacena, I., et al. "Capacitance–Voltage Investigation of Encapsulated Graphene/Silicon Solar Cells." IEEE Transactions on Electron Devices (2023).

DOI: 10.1109/ted.2023.3282917

[14] Gaberšček, M. (2022). Impedance spectroscopy of battery cells: Theory versus experiment. Current Opinion in Electrochemistry, 32, 100917.

DOI: 10.1016/j.coelec.2021.100917

[15] Chang, Yao-Wen, et al. "Charge-based capacitance measurement for bias-dependent capacitance." IEEE Electron Device Letters 27.5 (2006): 390-392.

DOI: 10.1109/led.2006.873368

[16] Almora, Osbel, et al. "On Mott-Schottky analysis interpretation of capacitance measurements in organometal perovskite solar cells." Applied Physics Letters 109.17 (2016).

DOI: 10.1063/1.4966127

[17] Gobbo, Carla, et al. "Effect of the ZnSnO/AZO interface on the charge extraction in Cd-free kesterite solar cells." Energies 16.10 (2023): 4137.

DOI: 10.3390/en16104137

[18] Matacena, Ilaria, et al. "Forward bias capacitance investigation as a powerful tool to monitor graphene/silicon interfaces." Solar Energy 226 (2021): 1-8.

DOI: 10.1016/j.solener.2021.08.016

[19] Heerens, W-C. "Application of capacitance techniques in sensor design." Journal of physics E: Scientific instruments 19.11 (1986): 897.

DOI: 10.1088/0022-3735/19/11/002

[20] Schroder, D.K. Semiconductor Material and Device Characterization, 3rd ed.; Wiley: Hoboken, NJ, USA, 2006.

[21] Hu, Chenming Calvin. "Modern Semiconductor Devices for Integrated Circuits." Part I: Electrons and holes in a semiconductor (2011).

[22] I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, S. Daliento, & A. Castellazzi, (2022). SiC MOSFET CV Characteristics with Positive Biased Drain. In Materials Science Forum (Vol. 1062, pp.653-657). Trans Tech Publications Ltd.

DOI: 10.4028/p-2tyqfr

[23] L. Maresca et al. Influence of the SiC/SiO 2 SiC MOSFET Interface Traps Distribution on C–V Measurements Evaluated by TCAD Simulations. IEEE Journal of Emerging and Selected Topics in Power Electronics 9.2 (2019): 2171-2179.

DOI: 10.1109/jestpe.2019.2940143

[24] Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2022, June). Experimental Analysis of CV and IV Curves Hysteresis in SiC MOSFETs. In Materials Science Forum (Vol. 1062, pp.669-675). Trans Tech Publications Ltd.

DOI: 10.4028/p-bzki64

[25] Matacena, Ilaria, et al. "SiC MOSFET CV Curves Analysis with Floating Drain Configuration." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

DOI: 10.4028/p-96q66n

[26] Matacena, Ilaria, et al. "Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

DOI: 10.4028/www.scientific.net/msf.1004.608

[27] Wei, Jiaxing, et al. "Interfacial damage extraction method for SiC power MOSFETs based on CV characteristics." 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). IEEE, 2017.

DOI: 10.23919/ispsd.2017.7988992

[28] Tsuji, Katsuhiro, et al. "Measurement of MOSFET CV curve variation using CBCM method." 2009 IEEE International Conference on Microelectronic Test Structures. IEEE, 2009.

DOI: 10.1109/icmts.2009.4814615

[29] Jouha, Wadia, et al. "Physical study of SiC power MOSFETs towards HTRB stress based on CV characteristics." IEEE Transactions on Device and Materials Reliability 20.3 (2020): 506-511.

DOI: 10.1109/tdmr.2020.2999029

[30] Matacena, Ilaria, et al. "SiC MOSFETs Capacitance study." e-Prime-Advances in Electrical Engineering, Electronics and Energy (2023): 100251.

DOI: 10.1016/j.prime.2023.100251

[31] Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2023, July). SiC MOSFETs Biased CV Curves: A Temperature Investigation. In Materials Science Forum (Vol. 1091, pp.31-36). Trans Tech Publications Ltd.

DOI: 10.4028/p-mqpk26

[32] Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2024). Frequency Investigation of SiC MOSFETs CV Curves with Biased Drain. Solid State Phenomena, 360, 145-149.

DOI: 10.4028/p-o37qxb

[33] Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2022, July). SiC/SiO 2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain. In 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp.1-5). IEEE.

DOI: 10.1109/ipfa55383.2022.9915748

[34] I. Matacena, A. Irace, S. Daliento and L. Maresca, "Investigation on Gate Capacitance Peak in SiC MOSFETs With Biased Drain," in IEEE Transactions on Electron Devices.

DOI: 10.1109/TED.2025.3638294