Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Abstract:

Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently can determine device lifetime. Most studies of BTI in SiC MOSFETs have characterized the threshold voltage (V_T) but not the interface trap density (N_it), leaving uncertainty about the relative contributions of carrier capture and trap creation to the V_T shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we measure N_it during positive bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in V_T and hysteresis using the triple-sense method [1], [2] for comparison with the N_it changes to evaluate whether the changes in N_it are responsible for the V_T and/or hysteresis changes, and demonstrate the utility of the technique for reliable characterization of V_T and hysteresis in SiC MOSFETs.

• Periodical: Key Engineering Materials (Volume 1057)
• Pages: 35-41
• DOI: https://doi.org/10.4028/p-JdLnD2
• Online since: May 2026
• Authors: Shane R. Stein*, Suman Das, Daniel J. Lichtenwalner, Sei Hyung Ryu
• Keywords: Bias Temperature Instability, Border Traps, Charge Pumping, Hysteresis, Interface Traps, Threshold Voltage (V_th), Triple Sense Method

References

[1] D. J. Lichtenwalner, "Demonstration of the Benefits of Measuring SiC MOSFET BTI using a Triple Sense Method," in 2025 IEEE International Reliability Physics Symposium (IRPS), Mar. 2025, p.1–5.

DOI: 10.1109/IRPS48204.2025.10983888

[2] JEP-184: Guideline for Evaluating Bias Temperature Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion, JEDEC Standards Publications. [Online]. Available: https://www.jedec.org/standards-documents/docs/jep184.

DOI: 10.3403/30499100

[3] A. J. Lelis et al., "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements," IEEE Trans. Electron Devices, vol. 55, no. 8, p.1835–1840, Aug. 2008.

DOI: 10.1109/TED.2008.926672

[4] T. Aichinger, G. Rescher, and G. Pobegen, "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs," Microelectronics Reliability, vol. 80, p.68–78, Jan. 2018.

DOI: 10.1016/j.microrel.2017.11.020

[5] J. H. Stathis, S. Mahapatra, and T. Grasser, "Controversial issues in negative bias temperature instability," Microelectronics Reliability, vol. 81, p.244–251, Feb. 2018.

DOI: 10.1016/j.microrel.2017.12.035

[6] T. Grasser et al., "The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps," IEEE Trans. Electron Devices, vol. 58, no. 11, Art. no. 11, Nov. 2011.

DOI: 10.1109/TED.2011.2164543

[7] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. 31, no. 1, Art. no. 1, Jan. 1984.

DOI: 10.1109/T-ED.1984.21472

[8] A. Salinaro et al., "Charge Pumping Measurements on Differently Passivated Lateral 4H-SiC MOSFETs," IEEE Trans. Electron Devices, vol. 62, no. 1, Art. no. 1, Jan. 2015.

DOI: 10.1109/TED.2014.2372874

[9] S. R. Stein, J. Kim, S. Das, D. J. Lichtenwalner, and S. Ryu, "Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress," in 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA: IEEE, Apr. 2024, p.1–5.

DOI: 10.1109/IRPS48228.2024.10529394

[10] F. Masin et al., "Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling," Journal of Applied Physics, vol. 130, no. 14, p.145702, Oct. 2021.

DOI: 10.1063/5.0057285

[11] T. Hatakeyama et al., "Impact of crystal faces of 4H-SiC in SiO2/4H-SiC structures on interface trap densities and mobilities," Appl. Phys. Express, vol. 12, no. 2, Art. no. 2, Feb. 2019.

DOI: 10.7567/1882-0786/aaf283

[12] H. Yoshioka, T. Nakamura, and T. Kimoto, "Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance," Journal of Applied Physics, vol. 111, no. 1, Art. no. 1, Jan. 2012.

DOI: 10.1063/1.3673572

[13] G. Rescher, G. Pobegen, T. Aichinger, and T. Grasser, "On the subthreshold drain current sweep hysteresis of 4H-SiC nMOSFETs," in 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA: IEEE, Dec. 2016, p.10.8.1-10.8.4.

DOI: 10.1109/IEDM.2016.7838392

[14] S. Dhar et al., "Inversion layer carrier concentration and mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors," Journal of Applied Physics, vol. 108, no. 5, Art. no. 5, Sep. 2010.

DOI: 10.1063/1.3484043