Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

Le Guan; Jia Li Gao; Jin Kui Chu

doi:10.4028/www.scientific.net/KEM.483.38

Paper Titles

Characterization of AlGaN/GaN Cantilevers Fabricated with Deep-Release Techniques
p.14

Dynamic Characteristics Measurement of Silicon Micro-Cantilever in Low Temperature Environment
p.18

Low Cost Fabrication of Micro Glass Cavities For MEMS Wafer Level and Hermetic Packaging
p.23

Study of Under Etching Characters of Si (100) in Surfactant Added TMAH
p.34

Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels
p.38

An Electrostatic Force Feedback Approach for Extending the Bandwidth of MEMS Vibratory Gyroscope
p.43

Fabrication of Large Area, 70 nm Pitch Nanograting Patterns by Nanoimprint Lithography Using Flexible Polymer Stamp
p.48

Effect of Micro-Injection Molding Process Parameters for Various Micro-Channels
p.53

Fabrication and Testing of SOG Structure Flat Heat Pipes with Triangle Grooves
p.58

HomeKey Engineering MaterialsKey Engineering Materials Vol. 483Design and System-Level Simulation of a Novel...

Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

Abstract:

The methods of on-chip integrated testing have a wide application with the development of the study for MEMS materials properties measurement in microscale. A novel on-chip integrated micro-tensile testing system is designed through system-level simulation based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films. The structure of testing instrument consists of V-beam electrothermal actuator, differential capacitance sensor, supporting spring and specimen. The capacitance signal is sensed and controlled by a second sigma-delta modulator circuit. The analytic macromodel of polysilicon thin film specimen considering geometric nonlinearity and the numerical reduced-order model of V-beam electrothermal actuator based on Krylov subspace projection are created separately and described in the MAST hardware language. The mechanical structure dimension size and circuit components parameters are determined and optimized according to system-level simulation. The computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable.