Optimization of TaSi2 Processing for 500 °C Durable SiC JFET-R Integrated Circuits

David J. Spry; Philip G. Neudeck; Carl W. Chang; Srihari Rajgopal; Jose M. Gonzalez

doi:10.4028/p-86f73x

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HomeKey Engineering MaterialsKey Engineering Materials Vol. 948Optimization of TaSi2 Processing for 500 °C...

Optimization of TaSi₂ Processing for 500 °C Durable SiC JFET-R Integrated Circuits

Abstract:

Experiments are described towards optimizing tantalum silicide (TaSi₂) interconnect metal film sputter-deposition and annealing in a manner compatible with the NASA Glenn two-layer interconnect silicon carbide (SiC) JFET-R IC process flow. Films deposited on 100 mm diameter wafers were investigated over a range of film thickness, sputter deposition, and post-deposition anneal conditions. An optimized process that achieved TaSi₂ films free of cracking and morphological defects while nearly halving post-anneal stress was developed and will be used for completing the interconnect fabrication of prototype IC Gen. 12 SiC JFET-R ICs.

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Periodical:

Key Engineering Materials (Volume 948)

Pages:

83-88

DOI:

https://doi.org/10.4028/p-86f73x

Citation:

Cite this paper

Online since:

June 2023

Authors:

David J. Spry*, Philip G. Neudeck, Carl W. Chang, Srihari Rajgopal, Jose M. Gonzalez

Keywords:

Film Stress, IC Fabrication, Sputter Deposition, Tantalum Silicide, TaSi₂

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Creative Commons CC BY 4.0

Citation:

* - Corresponding Author

References

[1] D. Spry et al., Mat. Sci. Forum 600-603 (2008) 1079-1082.

Google Scholar

[2] D. Spry et al., Electrochemical Soc. Trans. 69 (2015) 113-121.

Google Scholar

[3] P. Neudeck and D. Spry, Mat. Sci. Forum 1004 (2020) 1057-1065.

Google Scholar

[4] D. Spry, P. Neudeck, and C. Chang, Mat. Sci. Forum 1004 (2020) 1148-1155.

Google Scholar

[5] https://www.lesker.com/newweb/vacuum_systems/deposition_systems_pvd_cms18.cfm

Google Scholar

[6] https://k-space.com/document/product-specifications-ksa-mos/

Google Scholar

[7] https://tohotechnology.com/wp-content/uploads/2021/03/FLX-2320-S-Spec-Sheet-OFFICIAL.pdf

Google Scholar

[8] https://www.nanoscience.com/products/scanning-electron-microscopes/phenom-xl/

Google Scholar

[9] https://www.polytec.com/us/surface-metrology/products/optical-profilers

Google Scholar

[10] P. Townsend (1987), "Inelastic strain in thin films", PhD dissertation, Stanford University, Stanford.

Google Scholar

[11] P. Neudeck and D. Spry, Graphical Primer of NASA Glenn SiC JFET Integrated Circuit (IC) Version 12 Layout, https://ntrs.nasa.gov/citations/20190025716 (2019).

Google Scholar