150 mm SiC Engineered Substrates for High-Voltage Power Devices

Séverin Rouchier; Gweltaz Gaudin; Julie Widiez; Frédéric Allibert; Emmanuel Rolland; Kremena Vladimirova; Guillaume Gelineau; Nicolas Troutot; Christelle Navone; Guillaume Berre; Daphnée Bosch; Yen Lin Leow; Alain Duboust; Alexis Drouin; Jean Marc Bethoux; Romain Boulet; Audrey Chapelle; Enrica Cela; Guillaume Lavaitte; Adeline Bouville-Lallart; Laurent Viravaux; Florence Servant; Shivan Bhargava; Shawn Thomas; Ionut Radu; Christophe Maleville; Walter Schwarzenbach

doi:10.4028/p-mxxdef

Paper Titles

Review of Sublimation Growth of SiC Bulk Crystals
p.104

Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers
p.113

Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at Low Temperature < 1200°C for Photonic Applications
p.119

SiC Mass Commercialization: Present Status and Barriers to Overcome
p.125

150 mm SiC Engineered Substrates for High-Voltage Power Devices
p.131

Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition
p.136

Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material
p.140

Opening through 200 mm Silicon Carbide Epitaxy
p.146

Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing
p.155

HomeMaterials Science ForumMaterials Science Forum Vol. 1062150 mm SiC Engineered Substrates for High-Voltage...

150 mm SiC Engineered Substrates for High-Voltage Power Devices

Abstract:

Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high power electronics. Despite the continuously improving quality and supply of 4H-SiC substrates, the availability of such wafers is still insufficient. An advantageous opportunity is offered by the Smart Cut^TM technology with the integration of a very high quality SiC layer transferred to a low resistivity handle wafer. This bi-layer material enables a significant yield optimization and improvement of the device’s electrical performance. Moreover, an additional key feature of the Smart Cut^TM technology is the possibility to re-use multiple times the donor wafer, leading to reduced manufacturing costs and enabling the high volume production of SiC wafers. In this paper we report the latest advances in the development of such so called SmartSiC^TM substrates.

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Periodical:

Materials Science Forum (Volume 1062)

Pages:

131-135

DOI:

https://doi.org/10.4028/p-mxxdef

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Online since:

May 2022

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Keywords:

Low Resistivity, SiC Layer Transfer, SmartCut^TM, SmartSiC^TM

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References

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