Materials Science Forum Vol. 1062

Abstract: Impurity incorporation during vapor-phase epitaxy on stepped surfaces was modeled by classifying rate-limiting processes into i) surface diffusion, ii) step kinetics, and iii) segregation. Examples were shown for i) desorption-limited Al incorporation during chemical vapor deposition (CVD) of (0001) SiC, ii) preferential desorption of C atoms from kinks during CVD of Al-doped (000-1) SiC, and iii) segregation-limited C incorporation during metalorganic vapor-phase epitaxy of (0001), (000-1), and (10-10) GaN.

Abstract: In view of obtaining a step bunched morphology on large 4H-SiC surfaces, a sandwich configuration is investigated. A piece of silicon is melted between two 4H-SiC 4° off wafers, allowing a better spreading of the liquid than a Si drop approach. This successfully leads to highly step-bunched surfaces, though with irregular steps. The most regular step and terrace stuctures were found to be the result of epitaxial growth via a dissolution-precipitation process occuring from the edges to the center of the wafers. This is probably caused by radio-frequency induced electromagnetic convection within liquid Si. This process is quenched when using smaller liquid thickness.

Abstract: The yield of high power 4H-SiC Trench-MOSFET devices, especially for those with large chip area, is largely dependent on the quality of the underlying epitaxial layers and therefore low densities of critical defects are of utmost importance. Different growth conditions for the deposition of epitaxial layers were investigated to reduce the impact of defects on electrical device performance. For this investigation, 12 μm thick n-type epitaxial layers were grown varying growth rates for the buffer and the drift layer in a warm-wall chemical vapor deposition reactor. The defects in the epitaxial layers were characterized utilizing surface microscopy as well as ultraviolet photoluminescence techniques. A quantitative comparison of surface defects and crystallographic defects between the different growth conditions was conducted with these methods. The impact of the growth conditions on the formation of critical defects is discussed in detail. The reduction of critical defects, which resulted in an increase of the predicted die yield, as well as an outlook on future investigations, is discussed.

Abstract: In this work, the effect of high temperature molten KOH wet etching on GaN/AlGaN epilayer has been investigated for different family of dislocations. The high etching temperature (up to 510°C) allows a good definition of the pits, making easy the observation and the counts. Such high temperature will allow a detailed study on the statistical distribution of the dislocations on whole wafer by optical microscope for screw/mixed dislocation. A comparison on dislocation density between AlGaN/GaN structure grown on Si (111) substrate and 4H-SiC substrate has been performed.

Abstract: This work investigates the 3C-SiC heteroepitaxial growth on silicon substrates having a wide variety of orientations, i.e. (100) on axis and 2°off, (111), (110), (211), (311), (331), (510), (553) and (995). All the 3C-SiC layers were grown using the same two-step CVD process with a growth rate of 2 μm/h. According to X-ray diffraction characterizations, direct heteroepitaxy (layer having exactly the same orientation as the substrate) was successful on most of the Si substrates except for (110) one which was the only orientation leading to obvious polycrystalline deposit. Each layer led to a specific surface morphology, the smoothest being the ones grown on Si (100)2°off, and (995) substrates. None of these layers cracked upon cooling though those grown on Si (111), (211) and (553) substrates were highly bowed.

Abstract: The fabrication of novel semiconductor seed crystals using hetero-epitaxial growth on substrates such as Si, sapphire, and SiC, which have been successfully grown to large diameter and high quality, is very attractive as a breakthrough technology. However, a critical issue in heteroepitaxial growth is the formation of cracks due to thermal stress caused by the difference in the thermal expansion coefficient between the substrate and the growth layer during the cooling process after growth. In this study, we propose a method to reduce thermal stress by using a "Flexible substrate," which is a substrate with mechanical flexibility enhanced by removing more than 80% of its volume with periodic through holes. Using this method, we obtained an AlN hetero-epitaxial growth layer with absolutely no cracks observed. This method is applicable not only for AlN on SiC but also for the fabrication of various new semiconductor materials.

Abstract: In this work the intrinsic and induced defects related to the mechanical strength of 4H-SiC wafer have been investigated by considering substrates having different dislocation density and subjected to different treatments such as thinning process and high temperature bulk and laser annealing. Three point bending test has been performed on die extracted from the substrates in order to calculate the stress σ the die can withstand at breakage (flexural strength). The variation of intrinsic defect density seems does not act to modify the material flexural strength. Conversely, a considerable correlation between the induced defect density and flexural strength has been found.

Abstract: The excellent material properties of the wide band gap semiconductor SiC are accompanied by challenges in device processing. Of particular importance is the incomplete activation of implanted Al acceptors after high-temperature annealing. In this work, we present a novel approach in applying the differential-capacitance method to lateral MOS capacitors, where systematic errors in its characterization are reduced by introducing a buried current-spreading layer. We find that the implantation of an additional current-spreading layer significantly reduces series resistance effects and enables a reliable capacitance-voltage measurement of low dopant concentrations of p-type wells in n-type epitaxial layers. The measurement of an Al box-like profile implanted at 500 °C and resulting in a doping concentration of 3·10¹⁷ cm^-3 shows full activation after annealing at 1800 °C for 30 minutes.

Abstract: An alternative low thermal budget silicon carbide syntheses route is presented. The method is based on self-propagating high-temperature synthesis of binary silicon-carbon-based reactive mul­tilayers. With this technique, it is possible to obtain cubic polycrystalline silicon carbide at relatively low annealing temperatures by a solid state reaction. The reaction starts above 600 °C. The transformation process proceeds in a four-step process. The reaction enthalpy was determined to be (-70 ± 4) kJ/mol.