Materials Science Forum Vol. 1062

Abstract: It is known that generation of interfacial dislocation on SiC epitaxy depends mainly on misfit strain between substrate and the epilayer. In this paper, we investigate the impact of temperature profile, doping profile of the epilayer and resistivity of the substrates on the formation of interfacial dislocation in epilayers. Our preliminary results show that thermal profile during the epitaxy plays a key role in formation of interfacial dislocations in epilayers. We demonstrated reduction or elimination of interfacial dislocation in epilayers by optimizing the temperature profile of the wafers during the epitaxial growth.

Abstract: The review on bulk growth of SiC includes a basic overview on the widely used physical vapor transport method for processing of 4H-SiC boules as well as the discussion of three current research topics: (a) Sublimation bulk growth of large area, freestanding cubic SiC, (b) in-situ Visualization of the PVT Process using 2D and 3D X-ray based imaging and (c) prediction of dislocation formation and motion in SiC using a continuum model of dislocation dynamics (CDD).

Abstract: Screw-type dislocations like micropipes (MP) and threading screw dislocations (TSD) are prohibiting the function or at least diminishing the efficiency of electronic devices based on silicon carbide (SiC). Therefore, it is essential to characterize wafers in an efficient and fast manner. Molten potassium hydroxide (KOH) etching or white-beam X-ray topography (SWXRT) are either destructive or not economically viable for an in-depth characterization of every wafer of one SiC crystal. Birefringence microscopy is being utilized as a fast and non-destructive characterization method. Instead of microscopic setups, commercially available flat-bed scanners equipped with crossed polarizer foils can be used for fast large-area scans. This work investigates the feasibility of such a setup regarding the detection rate of MPs and TSDs. The results of a full-wafer mapping are compared with birefringence microscopy and KOH etching. In the investigated sample clusters of MPs caused by a polytype switch in the beginning of the growth could be identified by both birefringence microscopy and the flat-bed scanner setup, as well as small angle grain boundaries and TED arrays. However, the resolution of the scanner was not sufficient to identify TSDs. Nevertheless the setup proves to be an easy-to-setup and cheap characterization method, able to quickly identify defect clusters in 4H-SiC wafers.

Abstract: 3C-SiC films have been grown on [100] n-doped Si substrates in a horizontal cold wall CVD reactor. Without the use of plasma enhancement, the precursors silane and propane are used to deposit silicon carbide films at T < 1200°C. The structure of the grown films has been investigated via FESEM, XRD and Raman spectroscopy. It has been found that the growth rates are between 200 and 300 nm/h. Additionally, structural analysis give evidence of polycrystalline phases. Reasons for that could be insufficient cracking of the precursors and homogenous nucleation of Si species in the gas phase.

Abstract: In an increasingly electrified technology driven world, power electronics is central to the entire clean energy manufacturing economy. Silicon (Si) power devices have dominated power electronics due to their low cost volume production, excellent starting material quality, ease of fabrication, and proven reliability. Although Si power devices continue to improve, they are approaching their operational limits primarily due to their relatively low bandgap, critical electric field, and thermal conductivity that result in high conduction and switching losses, and poor high temperature performance. Silicon Carbide’s (SiC) compelling efficiency and system benefits have led to significant development efforts over the last two decades and today planar and trench MOSFETs, and JFETs are commercially available from several vendors as discrete components or in high power modules in the of 650 V to 1700 V voltage range. High impact application opportunities, where SiC devices are displacing their incumbent Si counterparts, have emerged and include automotive and rail power electronics with reduced losses and reduced cooling requirements; novel data center topologies with reduced cooling loads and higher efficiencies; variable frequency drives for efficient high power electric motors at reduced overall system cost; more efficient, flexible, and reliable grid applications with reduced system footprint; and “more electric aerospace” with weight, volume, and cooling system reductions contributing to energy savings. In particular, SiC insertion in electric vehicles brings major competitive advantages and is a volume application opportunity that can spur manufacturing economies of scale and lower system costs. As SiC continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. It should be noted that in many applications, insertion of SiC reduces overall system cost compared to Si even though SiC devices can cost 2-3 more than their Si counterparts. This is due to the passive component and cooling system simplifications enabled by the efficient high frequency SiC operation. In this paper, we will review key aspects of SiC technology and discuss overcoming barriers to mass commercialization.

Abstract: Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high power electronics. Despite the continuously improving quality and supply of 4H-SiC substrates, the availability of such wafers is still insufficient. An advantageous opportunity is offered by the Smart Cut^TM technology with the integration of a very high quality SiC layer transferred to a low resistivity handle wafer. This bi-layer material enables a significant yield optimization and improvement of the device’s electrical performance. Moreover, an additional key feature of the Smart Cut^TM technology is the possibility to re-use multiple times the donor wafer, leading to reduced manufacturing costs and enabling the high volume production of SiC wafers. In this paper we report the latest advances in the development of such so called SmartSiC^TM substrates.

Abstract: Tantalum carbide (TaC) coating, produced in an ultrahigh temperature chemical vapor deposition (CVD) process, exhibited high thermal and chemical stabilities, low emissivity, and high purity. Low emissivity of 0.3~0.43 was measured on TaC coating at 1000°C and compared with the one of SiC coating. As revealed in both simulation and experiment, the low emissivity of TaC coatings not only improves temperature uniformity in the SiC PVT process, but also reduces power consumption in both SiC crystal growth and GaN epitaxial deposition. The results provide important guidance to process tuning when switching from a conventional graphite or SiC-coated component to its TaC-coated counterpart.

Abstract: The present experimental study demonstrates the feasibility of Vanadium doping of 3CSiC hetero-epitaxial material. Some of Vanadium incorporation trends as well as the influence of Vanadium doping on 3C-SiC resistivity are observed.

Abstract: In this paper, the performance of a new CVD reactor (called PE1O8) designed by LPE and developed in the European project REACTION to process uniform 4H-SiC homoepitaxy on 200 mm substrate is reported. Its tunable multi-zone injection system and new gas delivery configuration ensure the uniform gas distribution throughout the substrate. Excellent thickness and doping uniformity on 200 mm substrates are achieved with run-to-run variation less than 1.4% and 5.6% respectively.

Abstract: The present paper shows a new fixed abrasive bond-grit formulation aimed for best-in-class, low-cost and high-quality finished SiC wafer surfaces. Grinding wheels manufactured with this technology can accomplish ultra-smooth SiC (Ra = 0.55 nm and TTV < 1 μm) surfaces due to their unique bonding structure and their tailored grit size. Additionally, SiC wafers ground with these wheels exhibit reduced sub-surface crystal damage, mirror-like polished surface and improved wafer geometry while both the grinding forces and the wheel wear are kept low.