Materials Science Forum Vol. 1062

Abstract: Silicon dioxide (SiO₂) layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N₂O were studied to identify the key factors influencing the channel mobility and threshold voltage stability in lateral implanted 4H-SiC MOSFETs. Cyclic gate bias stress measurements allowed to separate the contributions of interface states (N_it) and near interface oxide traps (NIOTs) in the two oxides. The reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~1nm) and carbon-related defects (<1nm) at the interface, as could be demonstrated by Electron Energy Loss Spectroscopy. The experimental results indicate that limiting the SiC re-oxidation during post-deposition annealing in MOSFET technology is a key factor to improve the mobility and threshold voltage stability.

Abstract: In this work the relationship between changes in wafer center bow after thinning process and the wafer morphology has been shown. KOH wet etching allowed the observation and counting of dislocation in 4H-SiC substrate. In deep a correspondence between changes in wafer center bow and the dislocation density of the SiC substrate has been observed. By using a counting software, a relationship with the basal plane dislocation and center bow has also been observed.

Abstract: A technical methodology of fabrication of hierarchically scaled multitude graphene nanogratings with varying pitches ranging from the micrometer down to sub 40 nm scale combined with sub 10 nm step heights on 4H and 6H semi-insulating SiC for length scale measurements is proposed. The nanogratings were fabricated using electron-beam lithography combined with dry etching of graphene, incorporating a standard semiconductor processing technology. A scientific evaluation of critical dimension, etching step heights, and surface characterization of graphene nanograting on both polytypes were compared and evaluated.

Abstract: Wafer scratching from handling and processing can impact the performance of devices grown on a substrate. Knowledge of process conditions and modeling of scratches on wafers can be used to elucidate the root cause of scratches so that they can be eliminated.

Abstract: Within this paper, we will present the results of a study on the ohmic contact formation process with nanosecond (ns) pulsed UV lasers. For the study we compared two laser processes: The base line process with a 100-300 ns pulsed laser with Gaussian beam profile and the 3D-Micromac AG process with a 50-100 ns pulsed laser with top hat beam profile. The forward voltage characteristics at wafer level was analyzed and proves a clear benefit of the top hat laser process. Besides, the forward voltage characteristics of a second run was performed to analyze the influence of increasing energy density to the electrical characteristic of heat sensitive front side structures. Also with high energy density no negative influence could be detected.

Abstract: P-type Ti/Al-based contact vias of different sizes but identical processing were electrically characterized using linear transfer length method (TLM) patterns and metal-oxide-semiconductor (MOS) transistors. While the TLM patterns and MOS transistors with large vias follow ohmic contact behavior, Schottky contact properties were observed for smaller contact via dimensions. Focused ion beam (FIB) analysis of the contact vias verified the presence of Ti₃SiC₂ on large 66 μm x 25 μm contact vias and its absence on smaller 16 μm x 3 μm ones, correlating its absence with the electrical Schottky properties.

Abstract: A systematic study is presented into the impact of a P₂O₅ surface passivation treatment, carried out prior to the deposition of a high refactory metal contact to 3.3 kV JBS diodes. Electrical results from Mo, W and Nb diodes reveal that those diodes that undergo the treatment have a major leakage current reduction, most significantly by 3.5 orders of magnitude to 1.5×10^-6 A.cm^-2 for treated W diodes. When applied to fully optimized 3.3 kV Mo/SiC JBS diodes, the P₂O₅ surface passivation treatment reduces the apparent barrier height, as well as the leakage current. SIMS analysis reveals that during the treatment, phosphorous diffuses into the top 10 nm of the SiC, achieving a peak density of 10¹⁹ cm^-3, while XPS results suggest some of this diffuses into the contact metal during the contact anneal, altering the SBH. TCAD simulations help give more insight into band diagram changes at the Schottky interface, where the partial activation of the phosphorous ions is shown to alter the Schottky barrier, promoting a thermionic field emission conduction, effectively lowering the barrier height at the interface in Mo/4H-SiC diodes.

Abstract: Silicon Carbide (SiC) has been demonstrated as both a bio- and neuro-compatible wide-band-gap semiconductor with a high thermal conductivity and magnetic susceptibility and may be potentially compatible with human brain tissue. Two single-crystal, solid-state forms of SiC have been used to create monolithic intracortical neural implants (INI) without using physiologically exposed metals or polymers, thus eliminating many known reliability challenges in-vivo through a single, homogenous material. Amorphous SiC (a-SiC) was used to insulate 16-channel functional INI and the electrochemical and MRI compatibility (7T) performance were measured. 4H-SiC interfaces were fabricated using homoepitaxy,alternating epitaxial films of n-type and p-type forming an isolating PN junction which prevents substrate leakage current between the 16 adjacent electrodes and traces fabricated which were formed using deep-reactive ion etching (DRIE). 3C-SiC interfaces were fabricated in a similar fashion, but the epitaial conductive layers were grown on on both bulk crystalline (100) silicon and SOI wafers. In both cases a conformal coating of a-SiC was used as the top-side insulator and windows opened using RIE to allow electrochemical interaction. Electrochemical charaterization achieved through electrochemcial impedance spectroscopy (EIS) and cyclic voltammetry (CV) indicates performance on par, or exceeding, that of Pt reference electrodes with the same form fit. While magnetic resonance imaging (MRI) is an essential, non-contact method used to investigate issues with the nervous system, the high field MRI (e.g., 3 T and higher) necessary for proper diagnosis can be a safety issue for patients with INI due to inductive coupling between the powerful electromagnetic fields and the implanted device. This results in having to use lower electromagnetic field power (less than 1.5T), and therefore lower resolution, which hinders diagnostic prognosis for these patients. In this work the MRI compliance of epitaxial, monolithic SiC INI was studied. The specific absorption rate (SAR), induced heating, and image artifacts caused by the portion of the implant within a brain tissue phantom located in a 7 T small animal MRI machine were estimated and measured via finite element method (FEM) and Fourier-based simulations. Both the simulation and experimental results revealed that free-standing 3C-SiC films had no observable image artifacts compared to silicon and platinum reference materials inside the MRI at 7 T while FEM simulations predicted an ~30% SAR reduction for 3C-SiC compared to Pt. These initial simulations and experiments indicate a SiC monolithic INI may effectively reduce MRI induced heating and image artifacts in high field MRI.

Abstract: This paper discusses a novel annealing technique for 4H-SiC implants which involves the use of pulsed XeCl laser (l=308 nm). In particular, an absorbing graphitic coating is used to protect the sample from surface atoms desorption or phase separation. Both conventional furnace annealing and laser annealing on P and Al implants, commonly employed for source and body in metal-oxide-semiconductor field-effect transistors (MOSFETs), were examined through Transmission Electron Microscopy (TEM), u-Raman spectroscopy and Scanning Electron Microscopy (SEM). It is shown that the implant activated through traditional thermal annealing at 1650 °C for 30 min has a large network of dislocation loops, while they do not appear to be present in the laser annealed implant. Through Raman spectroscopy and SEM investigations both the crystalline quality of the laser annealed sample and the integrity of the surface were attested.

Abstract: In this paper we present a novel tool layout for wet chemical processing of porous silicon carbide layers. The novel tool concept includes single side processing without edge exclusion. There is no need to contact the backside of the wafer. We show SEM cross sections of the porous layer made by different currents densities. With increased current density the porosity increases. After optimization of the process conditions, we achieve a layer thickness non-uniformity of 10%.