Polish Scratch Simulation vs. Polish Tool Type

Kevin Moeggenborg; Meong Keun Ju

doi:10.4028/p-wkn17q

Paper Titles

Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing
p.155

Charge Trapping Mechanisms in Nitridated SiO₂/ 4H-SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry
p.160

Impact of Dislocation on Warpage of Thinned 4H-SiC Wafers
p.165

Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC
p.170

Polish Scratch Simulation vs. Polish Tool Type
p.175

Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics
p.180

Via Size-Dependent Properties of TiAl Ohmic Contacts on 4H-SiC
p.185

Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a P₂O₅ Surface Passivation Treatment
p.190

The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation
p.195

HomeMaterials Science ForumMaterials Science Forum Vol. 1062Polish Scratch Simulation vs. Polish Tool Type

Polish Scratch Simulation vs. Polish Tool Type

Abstract:

Wafer scratching from handling and processing can impact the performance of devices grown on a substrate. Knowledge of process conditions and modeling of scratches on wafers can be used to elucidate the root cause of scratches so that they can be eliminated.

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Periodical:

Materials Science Forum (Volume 1062)

Pages:

175-179

DOI:

https://doi.org/10.4028/p-wkn17q

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Online since:

May 2022

Authors:

Kevin Moeggenborg*, Meong Keun Ju

Keywords:

Defect, Model, Polish, Scratch, Silicon Carbide, Wafer

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Creative Commons CC BY 4.0

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* - Corresponding Author

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