Materials Science Forum Vol. 1062

Abstract: Manufacturing of Silicon Carbide (SiC) based devices will soon require the accuracy and control typical of the advanced Si based nanoelectronics. As a consequence, the processes development will surely benefit of technology computer aided design (TCAD) tools dedicated to the current and future SiC process technologies. Plasma etching is one of the most critical and difficult process for optimization procedures in the micro/nanofabrication area, since the resultant 2D (e.g. in trenches) or 3D (e.g in holes) profiling is the consequence of the complex interactions between plasma and materials in the device structures. In this contribution we present a simulation tool dedicated to the etching simulation of SiC structures based on the sequential combination of a plasma scale global model and feature scale Kinetic Monte Carlo simulations. As an example of the approach validation procedure the simulations are compared with the characterization analysis of particular real process results.

Abstract: This work is focused on the fabrication of Titanium-based ohmic contacts by Laser Thermal Annealing (LTA) on n-type silicon carbide (4H-SiC). Their morphologies and electrical properties were studied by using two sets of parameters impacting the laser pulse overlap. With both sets, the ohmic contact transition was reached. The high overlap conditions produced a massive degradation of the contact morphology by leaving uncovered SiC. An optimisation of the annealing parameters was successfully performed by reducing the overlap. With the low overlap configuration, a specific contact resistance of 1.2×10^-4 Ω.cm² was measured for a fluence of 4.25 J.cm^-2 with a satisfying contact surface morphology.

Abstract: In this manuscript Ohmic contact formation at low annealing temperatures is demonstrated using shallow implantation technique. Remarkably, Ni Ohmic contacts with a specific contact resistivity of 1.9x10^-5 Ωcm² have been achieved at as-deposited condition. Smooth interfaces along with reduced Schottky barrier at the metal/SiC interface contributed to improved Ohmic performance at as-deposited and 450°C anneal conditions.

Abstract: Silicon Carbide (SiC) provides excellent characteristics such as superior thermal conductivity, high carrier mobility and extreme chemical stability in comparison with those of Silicon (Si). SiC is already showing significant device performance benefits in power devices, high performance communication, and LED lighting. However, SiC presents many challenges for wafer surface treatment because of its high hardness and remarkable chemical inertness. Today, mechanical polishing techniques on industrial batch CMP tools are the predominant methods for SiC wafer surface treatment, but material removal rate (MRR), surface defects and wafer flatness control are reaching fundamental limits with increasing wafer diameter. Batch processing typically results in a higher amount of surface scratches and defects, higher wafer to wafer variability, and higher wafer breakage rates. A unique single wafer chemical mechanical polishing (CMP) technique on 150mm n-doped, 4° off-axis, single crystal, 4H-SiC wafers was developed to create a virtually defect-free surface. A polishing head has been designed to manipulate polishing pressures at various zones of the wafer. This capability can modulate the removal thickness at each region on the wafer surface, resulting in a highly uniform wafer profile. Additionally, a CMP slurry has been formulated to maximize MRR from 2μm/hr to over 8.5μm/hr. Potassium permanganate has been selected as an oxidant and aluminum oxide particles as the abrasive. The oxidant concentration and abrasive content along with slurry pH level have also been optimized for ideal chemical and mechanical activity. Scratch-free wafer surfaces are observed with atomic force microscopy (AFM) and bright field (BF) and dark field (DF) inspection techniques. Roughness on the Si face is reduced to below 0.08nm. Total length of surface scratches was reduced to 10mm or less. Industrial metrics of wafer flatness, including total thickness variation (TTV) and local thickness variation (LTV) are modulated and improved. A test run completed on 25-wafers shows an overall 31% improvement of TTV post CMP process.

Abstract: Encapsulating SiC with a carbon layer (C-cap) is a widely used technique to avoid step bunching during post implantation annealing. In this work we propose a mechanism that explains the roughening that the surface unavoidably undergoes during annealing under the C-cap. We investigated the reactions occurring at the interface between 4H-SiC and the C-cap by scanning electron microscopy, energy-dispersive X-ray spectroscopy, and atomic force microscopy carried out at different stages of the sample processing: just after annealing, after C-cap removal in dry Oxygen, and after cleaning in buffered oxide etch solution. Our observations show that, even though the C-cap roughens for increasing annealing temperature and time, it is not visibly damaged even after 1950 °C 30 min annealing. After the C-cap removal the 4H-SiC surface was covered by a network of clusters that are eventually removed by buffered oxide etch solution. This occurrence suggests that, during the post-implantation annealing, the 4H-SiC surface decomposes and the escaped Si and C atoms are trapped inside the C-cap or at the interface between 4H-SiC and the C-cap. While C clusters are etched off in the dry O₂ atmosphere, the Si clusters oxidize and form SiO₂ nanoparticles which are finally etched by buffered oxide etch.

Abstract: Activation and compensation ratios feature the electrical doping efficiency of a semiconductor material by ion implantation. The estimation of these ratios requires a quantitative evaluation of the density of the implanted dopant in substitutional position and of the density of the compensator centers after the mandatory post implantation annealing treatment. In the case of Al⁺ ion implanted 4H-SiC, it is a common habit to determine acceptor density, compensator density and acceptor thermal ionization energy by fitting the curve of the drift holes temperature dependence with the charge neutrality equation. However, this strategy could lead to ambiguous results. In fact, this study shows several cases of Al⁺ ion implanted 4H-SiC of interest for electronic device fabrication, where at least two sets of such fitting outputs can reproduce the same experimental curve within the uncertainty of the data. Provided that a model for the carrier transport could be set-up, the contemporaneous fits of the temperature dependence of drift hole density and of drift hole mobility is proposed to alleviate the uncertainty of the estimated acceptor density, compensator density and acceptor thermal ionization energy.

Abstract: Post-growth thermal processing at higher temperature generates more BPDs (basal plane dislocations). It is observed that dislocation visibility in surface inspection tool images varies significantly even at comparable dislocation densities. Combination of dislocation decoration and light absorbance from SiC matrix by point defects or dopants has been proposed as a working hypothesis to explain dislocation visibility variations.

Abstract: A transient thermal network model is utilized to design and evaluate the transient thermal characteristics of power modules. Static test method identifies the transient thermal network model from the time response of the junction temperature, which is obtained by using the temperature dependency of I-V characteristics for power devices. This paper experimentally evaluates the effect of the sampling frequency and the resolution of the AD conversion on the accuracy of the obtained transient thermal network model. The high sampling frequency and the high resolution in the obtained time response of the junction temperature enable to clearly identify the transient thermal network model of the power module with the direct bonding copper substrate.

Abstract: Double-rhombic shaped single Shockley stacking faults (1SSFs) were considered to have a converted threading edge dislocation (TED) on the shallower side of the initial basal plane dislocation segments. However, the structural analysis using transmission electron microscopy (TEM) revealed other possible configuration of the double-rhombic 1SSFs expanded from basal plane dislocations (BPDs) of which both ends were connected with two TEDs.

Abstract: In this work, we study the impact of the dose rate on the electrical properties of aluminum (p-body, p⁺-body-contact) and phosphorous (n-source/drain) implanted 4H-SiC. We find no significant differences for dose rates ranging from 1×10¹¹ cm^-2s^-1 to 2−7×10¹² cm^-2s^-1. AFM scans across implanted and non-implanted regions after thermal oxidation and subsequent oxide etching reveal a clear dependence of the oxidation rate on the conduction type and doping concentration. In addition, we observe an increasing (decreasing) oxidation rate for increasing doping concentrations of the n-type (p-type) ion implanted areas.