Preface
Models for Impurity Incorporation during Vapor-Phase Epitaxy
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p.3
Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration
p.8
p.8
Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth
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p.13
High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer
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p.18
3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations
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p.23
A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AlN Bulk Crystal by Thermal Strain Relaxation Functionality
p.28
p.28
The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates
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p.33
Aluminum Activation in 4H-SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer
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Models for Impurity Incorporation during Vapor-Phase Epitaxy
Abstract:
Impurity incorporation during vapor-phase epitaxy on stepped surfaces was modeled by classifying rate-limiting processes into i) surface diffusion, ii) step kinetics, and iii) segregation. Examples were shown for i) desorption-limited Al incorporation during chemical vapor deposition (CVD) of (0001) SiC, ii) preferential desorption of C atoms from kinks during CVD of Al-doped (000-1) SiC, and iii) segregation-limited C incorporation during metalorganic vapor-phase epitaxy of (0001), (000-1), and (10-10) GaN.
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Periodical:
Materials Science Forum (Volume 1062)
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3-7
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Online since:
May 2022
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