Impact of Bias Temperature Instabilities on the Performance of Power Electronics Employing SiC MOSFETs

Abstract:

In this work a reliability study of SiC power MOSFETs working as switching elements in a DC-DC Boost converter circuit is discussed. A critical parameter for a high-performance operation is the stable characteristics of the transistors employed. However, charge trapping effects such as bias temperature instabilities can affect e.g. the threshold voltage of transistors and thus lead to a variation in circuit behavior and efficiency. Furthermore, a time-dependent drift of the threshold voltage (ΔVth) of the MOSFET over time can cause an increase of the on-resistance (RDS(ON)) too, and thus affect the static on-state power losses accordingly (PON). In this work, we use our physical reliability simulator Comphy to extract the threshold voltage drift of the transistor over time for various mission profiles for gate biases under device operation. Using the extracted ΔVth values from the simulator, we can reproduce the measured behavior of the DC-DC boost converter circuit. With the calibrated toolset, we can obtain the ΔVth values over a long operation time to predict the aged behavior of the circuit parameters employing Spice simulations, which could be beneficial for circuit design and lifetime prediction of the system.

• Periodical: Materials Science Forum (Volume 1092)
• Pages: 193-200
• DOI: https://doi.org/10.4028/p-7c79an
• Online since: June 2023
• Authors: Yoanlys Hernandez, Christian Schleich, Bernhard Stampfer, Tibor Grasser, Michael Waltl*
• Keywords: Bias Temperature Instability (BTI), Charge Trapping, DC-DC Boost Converter, Power MOSFET, Reliability Study, Spice Simulation

References

[1] L. F. Costa, G. Buticchi and M. Liserre, "Highly Efficient and Reliable SiC-Based DC-DC Converter for Smart Transformer," in IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp.8383-8392, Oct. 2017.

DOI: 10.1109/TIE.2017.2696481

[2] R. M. Burkart and J. W. Kolar, "Comparative η- ρ- σ Pareto Optimization of Si and SiC Multilevel Dual-Active-Bridge Topologies With Wide Input Voltage Range," in IEEE Transactions on Power Electronics, vol. 32, no. 7, pp.5258-5270, July 2017.

DOI: 10.1109/TPEL.2016.2614139

[3] M. Liserre, G. Buticchi, M. Andresen, G. De Carne, L. F. Costa and Z. -X. Zou, "The Smart Transformer: Impact on the Electric Grid and Technology Challenges," in IEEE Industrial Electronics Magazine, vol. 10, no. 2, pp.46-58, June 2016, doi: 10.1109/MIE.2016.2551418.[4] S. Raghavendran, K. S. Kumar, A. Tirupathi and C. B, in: 2020 3rd International Conference on Energy, Power and Environment: Towards Clean Energy Technologies, (2021), pp.1-6.

DOI: 10.1109/mie.2016.2551418

[5] R. Green, A. Lelis and D. Habersat: "Threshold-voltage bias-temperature instability in commercially-available SiC MOSFETs", Jpn. J. Appl. Phys., Vol. 55, (2016), p. 04EA03

DOI: 10.7567/JJAP.55.04EA03

[6] T. Aichinger, G. Rescher and G. Pobegen: "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs", Microelectronics Reliability, Vol. 80, (2018), pp.68-78.

DOI: 10.1016/j.microrel.2017.11.020

[7] J. A. O. González and O. Alatise: "A Novel Non-Intrusive Technique for BTI Characterization in SiC mosfets," in IEEE Transactions on Power Electronics, Vol. 34, no. 6, pp.5737-5747, (2019).

DOI: 10.1109/TPEL.2018.2870067

[8] H. Luo, F. Iannuzzo and M. Turnaturi: "Role of Threshold Voltage Shift in Highly Accelerated Power Cycling Tests for SiC MOSFET Modules," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 2, pp.1657-1667, (2020).

DOI: 10.1109/JESTPE.2019.2894717

[9] K. Puschkarsky, H. Reisinger, G. A. Rott, C. Schlünder, W. Gustin and T. Grasser, "An Efficient Analog Compact NBTI Model for Stress and Recovery Based on Activation Energy Maps," in IEEE Transactions on Electron Devices, vol. 66, no. 11, pp.4623-4630, Nov. 2019.

DOI: 10.1109/TED.2019.2941889

[10] Langpoklakpam, C.; Liu, A.-C.; Chu, K.-H.; Hsu, L.-H.; Lee, W.-C.; Chen, S.-C.; Sun, C.-W.; Shih, M.-H.; Lee, K.-Y.; Kuo and H.-C: "Review of Silicon Carbide Processing for Power MOSFET.", Crystals, (2022), Vol. 12, 245

DOI: 10.3390/cryst12020245

[11] Information on https://www.wolfspeed.com/tools-and-support/power/ltspice-and-plecs-models

[12] M. Waltl, "Ultra-Low Noise Defect Probing Instrument for Defect Spectroscopy of MOS Transistors," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp.242-250, June 2020.

DOI: 10.1109/TDMR.2020.2988650

[13] Langpoklakpam, C.; Liu, A.-C.; Chu, K.-H.; Hsu, L.-H.; Lee, W.-C.; Chen, S.-C.; Sun, C.-W.; Shih, M.-H.; Lee, K.-Y.; Kuo, H.-C. Review of Silicon Carbide Processing for Power MOSFET. Crystals 2022, 12, 245.

DOI: 10.3390/cryst12020245

[14] F. Yang, E. Ugur, S. Pu, B. Akin and M. Das: "Investigation of Aging's Effect on the Conduction and Switching Loss in SiC MOSFETs," 2019 IEEE Energy Conversion Congress and Exposition (ECCE), (2019), pp.6166-6173.

DOI: 10.1109/ECCE.2019.8912284

[15] Lelis, A.J.; Green, R.; Habersat, D.B. "SiC MOSFET threshold-stability issues". Mater. Sci. Semicond. Process. 2018, 78, 32-37

DOI: 10.1016/j.mssp.2017.11.028

[16] A. J. Lelis et al., "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements," in IEEE Transactions on Electron Devices, vol. 55, no. 8, pp.1835-1840, Aug. 2008.

DOI: 10.1109/TED.2008.926672

[17] A. J. Lelis, R. Green, D. B. Habersat and M. El, "Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs," in IEEE Transactions on Electron Devices, vol. 62, no. 2, pp.316-323, Feb. 2015, doi: 10.1109/TED.2014.2356172.[18] G. Rzepa et al.: "Comphy - a compact-physics framework for unified modeling of BTI" Microelectronics Reliability, (2018)

DOI: 10.1016/j.microrel.2018.04.002

[19] C. Schleich et al., "Physical Modeling of Bias Temperature Instabilities in SiC MOSFETs," 2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.20.5.1-20.5.4.

DOI: 10.1109/IEDM19573.2019.8993446

[20] C. Schleich, D. Waldhör, K. Waschneck, M. Feil, H. Reisinger, T. Grasser and M. Waltl: "Physical Modeling of Charge Trapping in 4H-SiC DMOSFET Technologies," in IEEE Transactions on Electron Devices, vol. 68, no. 8, pp.4016-4021, Aug. 2021.

DOI: 10.1109/TED.2021.3092295

[21] Y. Hernandez, B. Stampfer, T. Grasser and M. Waltl: "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies"; Crystals, Vol. 11, (2021), pp.1150-9.

DOI: 10.3390/cryst11091150

[22] J. Martin-Martinez, N. Ayala, R. Rodriguez, M. Nafria and X. Aymerich, "RELAB: A tool to include MOSFETs BTI and variability in SPICE simulators," 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), (2012), pp.249-252.

DOI: 10.1109/SMACD.2012.6339386

[23] K. Puschkarsky, H. Reisinger, W. Gustin, T. Grasser: "Voltage-Dependent Activation Energy Maps for Analytic Lifetime Modeling of NBTI Without Time Extrapolation"; IEEE Transactions on Electron Devices, Vol. 65, (2018), pp.4764-4771.

DOI: 10.1109/TED.2018.2870170

[24] J. O. Gonzalez and O. Alatise: "Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs," in IEEE Transactions on Industry Applications, Vol. 57, no. 2, pp.1664-1676, (2021).

DOI: 10.1109/TIA.2020.3045120