Stacking Fault Formation in Highly Doped 4H-SiC Epilayers during Annealing

Abstract:

Article Preview

Info:

Periodical:

Materials Science Forum (Volumes 433-436)

Edited by:

Peder Bergman and Erik Janzén

Pages:

253-256

Citation:

H. J. Chung et al., "Stacking Fault Formation in Highly Doped 4H-SiC Epilayers during Annealing", Materials Science Forum, Vols. 433-436, pp. 253-256, 2003

Online since:

September 2003

Export:

Price:

$38.00

[1] R. S. Okojie, M. Xhang, P. Pirouz, S. Tumkha, G. Jessen, and L. Brillson: Appl. Phys. Lett. Vol. 79 (2001), p.3056.

[2] B. J. Skromme, K. Palle, C. D. Poweleit, L. R. Bryant, W. M. Vetter, M. Dudley, K. Moore and T. Gehoski: Mat. Sci. Forum Vol. 389-393 (2002), p.455.

DOI: https://doi.org/10.4028/www.scientific.net/msf.389-393.455

[3] J. Q. Liu, H. J. Chung, T. Kuhr, Q. Li, and M. Skowronski: Appl. Phys. Lett. Vol. 80 (2002), p.2111.

[4] L. Dong, J. Schinitker, R. W. Smith, and D. J. Srolovitz: J. Appl. Phys. Vol. 83 (1998), p.217.

[5] M. H. Hong, A. V. Samant, and P. Pirouz: Mater. Sci. Forum Vol. 338-342 (2000), p.513 Fig. 6 High-resolution TEM image of a stacking fault in 6H-SiC epilayer.

DOI: https://doi.org/10.4028/www.scientific.net/msf.338-342.513

Fetching data from Crossref.
This may take some time to load.