Numerical Simulation and Optimization for 900V 4H-SiC DiMOSFET Fabrication

Sang Cheol Kim; Wook Bahng; Nam Kyun Kim; Eun Dong Kim; T. Ayalew; Tibor Grasser; Siegfried Selberherr

doi:10.4028/www.scientific.net/MSF.483-485.793

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HomeMaterials Science ForumMaterials Science Forum Vols. 483-485Numerical Simulation and Optimization for 900V...

Numerical Simulation and Optimization for 900V 4H-SiC DiMOSFET Fabrication

Abstract:

We report the simulation results of 25µm half cell pitch vertical type 4H-SiC DiMOSFET using the general-purpose device simulator MINIMOS-NT. The best trade-off between breakdown voltage and on-resistance in terms of BFOM is around 19MW/cm2 with a p-well spacing 5µm. The specific on -resistance, RON, sp, simulated with VGS=10V and VDS=1V at room temperature, is around 22.76mWcm2. An 900V breakdown voltage is simulated with ion-implanted edge termination.

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Periodical:

Materials Science Forum (Volumes 483-485)

Pages:

793-796

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.483-485.793

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Online since:

May 2005

Authors:

Sang Cheol Kim, Wook Bahng, Nam Kyun Kim, Eun Dong Kim, T. Ayalew, Tibor Grasser, Siegfried Selberherr

Keywords:

DIMOSFET, Edge Termination, MINIMOS-NT, Silicon Carbide (SiC)

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References

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