Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

H. Kawano; Tsunenobu Kimoto; Jun Suda; Hiroyuki Matsunami

doi:10.4028/www.scientific.net/MSF.483-485.809

Paper Titles

Numerical Simulation and Optimization for 900V 4H-SiC DiMOSFET Fabrication
p.793

4H-SiC DMOSFETs for High Speed Switching Applications
p.797

Realisation of Large Area 3C-SiC MOSFETs
p.801

4H-SiC Lateral RESURF MOSFETs on Carbon-Face Substrates
p.805

Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication
p.809

Analysis of Low On-Resistance in 4H-SiC Double-Epitaxial MOSFET
p.813

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET
p.817

Short-Channel Effects in 4H-SiC MOSFETs
p.821

Performance of SiC Cascode Switches with Si MOS Gate
p.825

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Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

Abstract:

Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.