Advanced Annealing Schemes for High-Performance SOI Logic Technologies
We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.
W. Lerch and J. Niess
T. Feudel "Advanced Annealing Schemes for High-Performance SOI Logic Technologies", Materials Science Forum, Vols. 573-574, pp. 387-400, 2008