Advanced Annealing Schemes for High-Performance SOI Logic Technologies

Thomas Feudel

doi:10.4028/www.scientific.net/MSF.573-574.387

Paper Titles

Ultra-Rapid Thermal Process for ULSIs
p.319

Advanced Millisecond Annealing Technologies and its Applications and Concerns on Advanced Logic LSI Fabrication Processes
p.325

Doping Strategies for FinFETs
p.333

RTP Requirements for CMOS Integration of Dual Work Function Phase Controlled Ni-FUSI (Fully Silicided) Gates with Simultaneous Silicidation of nMOS (NiSi) and pMOS (Ni-Rich Silicide) Gates on HfSiON
p.341

A Short History of Pattern Effects in Thermal Processing
p.355

Conduction Heating in RTP Fast, and Pattern-Independent
p.375

Advanced Annealing Schemes for High-Performance SOI Logic Technologies
p.387

Model Based Measurement in Advanced Rapid Thermal Processing
p.403

Short Time Thermal Processing: From Electronics via Photonics to Pipe Organs of the 17^th Century
p.417

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Advanced Annealing Schemes for High-Performance SOI Logic Technologies

Abstract:

We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.