Ultra-Rapid Thermal Process for ULSIs

Kyoichi Suguro

doi:10.4028/www.scientific.net/MSF.573-574.319

Paper Titles

Extended Defects Evolution in Pre-Amorphised Silicon after Millisecond Flash Anneals
p.269

Modeling and Simulation of Advanced Annealing Processes
p.279

Vacancy Engineering – An Ultra-Low Thermal Budget Method for High-Concentration 'Diffusionless' Implantation Doping
p.295

Ultra-Shallow Junction Formation Using Rapid Thermal Processing
p.305

Ultra-Rapid Thermal Process for ULSIs
p.319

Advanced Millisecond Annealing Technologies and its Applications and Concerns on Advanced Logic LSI Fabrication Processes
p.325

Doping Strategies for FinFETs
p.333

RTP Requirements for CMOS Integration of Dual Work Function Phase Controlled Ni-FUSI (Fully Silicided) Gates with Simultaneous Silicidation of nMOS (NiSi) and pMOS (Ni-Rich Silicide) Gates on HfSiON
p.341

A Short History of Pattern Effects in Thermal Processing
p.355

HomeMaterials Science ForumMaterials Science Forum Vols. 573-574Ultra-Rapid Thermal Process for ULSIs

Ultra-Rapid Thermal Process for ULSIs

Abstract:

This paper reports on the ultra-rapid thermal annealing of next generation MOSFETs. In ultra-rapid thermal annealing, the most important issue is to achieve a good balance between electrical activation and impurity diffusion. Another issue of annealing implantation damages is also discussed: Optimized annealing combined with millisecond annealing and conventional halogen lamp annealing is necessary for annealing out defects at end-of range region. Application possibilities of millisecond annealing for deep junction activation and oxidation are also discussed.