A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures

Abstract:

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A novel method based on the analysis of the C-V hysteresis change with increasing charge release time is proposed. The presence of a band of deep traps was demonstrated using this method in 3C-SiC samples. The same band of deep traps was also observed using photo-electric measurements of barrier height EBS in the same samples.

Info:

Periodical:

Materials Science Forum (Volumes 645-648)

Edited by:

Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller

Pages:

523-526

DOI:

10.4028/www.scientific.net/MSF.645-648.523

Citation:

T. Gutt et al., "A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures", Materials Science Forum, Vols. 645-648, pp. 523-526, 2010

Online since:

April 2010

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Price:

$35.00

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