A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures
A novel method based on the analysis of the C-V hysteresis change with increasing charge release time is proposed. The presence of a band of deep traps was demonstrated using this method in 3C-SiC samples. The same band of deep traps was also observed using photo-electric measurements of barrier height EBS in the same samples.
Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller
T. Gutt et al., "A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures", Materials Science Forum, Vols. 645-648, pp. 523-526, 2010