A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures

Tomasz Gutt; Henryk M. Przewlocki; Mietek Bakowski

doi:10.4028/www.scientific.net/MSF.645-648.523

Paper Titles

Improved Electrical Properties of SiC-MOS Interfaces by Thermal Oxidation of Plasma Nitrided 4H-SiC(0001) Surfaces
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Improved 4H-SiC MOS Interface Produced by Oxidized-SiN Gate Oxide
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Investigation of Oxide Films Prepared by Direct Oxidation of C-Face 4H-SiC in Nitric Oxide
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Experimental Identification of Extra Type of Charges at SiO₂/SiC Interface in 4H-SiC
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A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures
p.523

EDMR and EPR Studies of 4H SiC MOSFETs and Capacitors
p.527

Electrical Properties and Gas Sensing Characteristics of the Al₂O₃/4H SiC Interface Studied by Impedance Spectroscopy
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Crystalline Quality of Channel Regions in SiC Buried Gate Static Induction Transistors (SiC-BGSITs)
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Study of the Evolution of Basal Plane Dislocations during Epitaxial Growth: Role of the Surface Kinetics
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HomeMaterials Science ForumMaterials Science Forum Vols. 645-648A C-V Method of Slow-Switching Interface Traps...

A C-V Method of Slow-Switching Interface Traps Identification in Silicon Carbide MOS Structures

Abstract:

A novel method based on the analysis of the C-V hysteresis change with increasing charge release time is proposed. The presence of a band of deep traps was demonstrated using this method in 3C-SiC samples. The same band of deep traps was also observed using photo-electric measurements of barrier height EBS in the same samples.

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Silicon Carbide and Related Materials 2009

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Periodical:

Materials Science Forum (Volumes 645-648)

Pages:

523-526

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.645-648.523

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Online since:

April 2010

Authors:

Tomasz Gutt, Henryk M. Przewlocki, Mietek Bakowski

Keywords:

Barrier Height, C-V Characterization, Interface Trap

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References

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