Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor
This paper presents a study on a SiC JFET leg of a 3-leg Voltage Source Inverter (VSI). The switching curves obtained with the JFET working in free wheeling mode are shown to point out drain-to-gate interaction effects. Indeed, during the drain-source voltage variations, the JFET gate-source voltage can have considerable variations, because of the electrical coupling induced by the gate-drain capacitance Cgd. When the gate-source voltage variation becomes too negative, there is a risk of occurrence of the phenomenon of punch-through in the gate-source junction. Conversely, when it is enough positive, the JFET may conduct and lead to a leg short-circuit. To decrease these undesired effects for the JFET legs and consequently for the SiC JFET inverter, an external gate-source capacitor is used. This solution is studied and optimized by simulation on an inverter leg.
Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller
O. Berry et al., "Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor", Materials Science Forum, Vols. 645-648, pp. 957-960, 2010