Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor

Olivier Berry; Youness Hamieh; Stéphane Raël; Farid Meibody-Tabar; Sébastien Vieillard; Dominique Bergogne; Hervé Morel

doi:10.4028/www.scientific.net/MSF.645-648.957

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HomeMaterials Science ForumMaterials Science Forum Vols. 645-648Minimization of Drain-to-Gate Interaction in a SiC...

Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor

Abstract:

This paper presents a study on a SiC JFET leg of a 3-leg Voltage Source Inverter (VSI). The switching curves obtained with the JFET working in free wheeling mode are shown to point out drain-to-gate interaction effects. Indeed, during the drain-source voltage variations, the JFET gate-source voltage can have considerable variations, because of the electrical coupling induced by the gate-drain capacitance Cgd. When the gate-source voltage variation becomes too negative, there is a risk of occurrence of the phenomenon of punch-through in the gate-source junction. Conversely, when it is enough positive, the JFET may conduct and lead to a leg short-circuit. To decrease these undesired effects for the JFET legs and consequently for the SiC JFET inverter, an external gate-source capacitor is used. This solution is studied and optimized by simulation on an inverter leg.

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Materials Science Forum (Volumes 645-648)

Pages:

957-960

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.645-648.957

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Online since:

April 2010

Authors:

Olivier Berry, Youness Hamieh, Stéphane Raël, Farid Meibody-Tabar, Sébastien Vieillard, Dominique Bergogne, Hervé Morel

Keywords:

Junction Field Effect Transistor (JFET), Punch-Through, Switching Characteristics

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References

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