Circuit Modeling of Vertical Buried-Grid SiC JFETs

Georg Tolstoy; Dimosthenis Peftitsis; Jang Kwon Lim; Mietek Bakowski; Hans Peter Nee

doi:10.4028/www.scientific.net/MSF.645-648.965

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HomeMaterials Science ForumMaterials Science Forum Vols. 645-648Circuit Modeling of Vertical Buried-Grid SiC JFETs...

Circuit Modeling of Vertical Buried-Grid SiC JFETs

Abstract:

The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

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Materials Science Forum (Volumes 645-648)

Pages:

965-968

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.645-648.965

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Online since:

April 2010

Authors:

Georg Tolstoy, Dimosthenis Peftitsis, Jang Kwon Lim, Mietek Bakowski, Hans Peter Nee

Keywords:

Junction Field Effect Transistor (JFET), MEDICI, Spice Model

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References

[1] J-K Lim, M. Bakowski and H-P Nee, Design and gate drive considerations for epitaxial 1. 2 kV buried grid normally-on and normally-off JFETs for operation at 250°C, ICSCRM 2009, 11-16 October 2009, Nuremberg.

DOI: 10.4028/www.scientific.net/msf.645-648.961

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[2] Y. Wang, et al, SPICE Model of SiC JFETs for Circuit Simulations, IEEE Compel Workshop 2006, 16-19 July 2006, Troy NY.

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[5] PSpice Reference Guide Fig. 7: Medici and numerical calculations results for I-V characteristics with BETA fitting.

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