Effect of ON-State Stress on SiC DMOSFET Subthreshold I-V Characteristics

Aivars J. Lelis; Ronald Green; Daniel B. Habersat; Neil Goldsman

doi:10.4028/www.scientific.net/MSF.645-648.983

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HomeMaterials Science ForumMaterials Science Forum Vols. 645-648Effect of ON-State Stress on SiC DMOSFET...

Effect of ON-State Stress on SiC DMOSFET Subthreshold I-V Characteristics

Abstract:

We have observed a noticeable increase in the instability of the I-V characteristics following an ON-state current stress, especially in the subthreshold region. An increased stretch-out and negative shift can give rise to increased leakage current in the OFF-state if proper precautions are not met to provide a proper margin for the threshold voltage. State-of-the-art 50-A MOSFETs exhibit less instability than previous 20-A devices, and devices that run hotter show a larger degradation.

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Materials Science Forum (Volumes 645-648)

Pages:

983-986

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https://doi.org/10.4028/www.scientific.net/MSF.645-648.983

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Online since:

April 2010

Authors:

Aivars J. Lelis, Ronald Green, Daniel B. Habersat, Neil Goldsman

Keywords:

Charge Trapping, Current Stress, DMOSFET, Leakage Current

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