Physics of Hysteresis in MESFET Drain I-V Characteristics: Simulation Approach

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The two-dimensional device simulator, MediciTM, was used to simulate 4H silicon carbide (4H-SiC) n-channel power metal semiconductor field effect transistors (MESFETs) with 0.5 µm gate length with and without p-type buffer layer between the n-channel and the semi-insulating (SI) substrate. The devices, which have previously been fabricated and characterized experimentally, have ion-implanted n+ source and drain ohmic contact regions. The simulations were performed with transient 30 V amplitude symmetrical triangular pulse with 30 s pulse width. Simulations show that hysteresis in drain I-V curves of MESFETs is due to substrate traps and source/drain implant damage traps. The hysteresis is caused by trapping and emission of channel electrons by the traps as VDS rises from 0 V to VDS(max) and as VDS falls from VDS(max) back to 0 V. This leads to difference in trap occupation, and hence difference in channel electron concentration as VDS rises and falls. This finally leads to difference in drain-source current (IDS) at a given VDS for a given VGS as VDS rises and falls, giving rise to the hysteresis in the I-V curves.

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Materials Science Forum (Volumes 645-648)

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945-948

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April 2010

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© 2010 Trans Tech Publications Ltd. All Rights Reserved

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[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] ___ VDS=19V forward curve _ _ _ VDS=19V return curve NT = 1E17 cm �3 VGS= −20V Empty Trap Concentration (#/cubic cm) 1 E 16 Distance from device surface, y (um) Fig. 5. Empty trap distribution (trap occupation) for MESFET with substrate traps only. Trap density NT = 1E17 cm−3.

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