Effects of Process Variations on Silicon Carbide Devices for Extreme Environments

Hassan Habib; Nicolas G. Wright; Alton B. Horsfall

doi:10.4028/www.scientific.net/MSF.679-680.401

Paper Titles

Effect of Increased Oxide Hole Trap Density due to Nitrogen Incorporation at the SiO₂/SiC Interface on F-N Current Degradation
p.382

Energy Band Structure of SiO₂/4H-SiC Interfaces and its Modulation Induced by Intrinsic and Extrinsic Interface Charge Transfer
p.386

Improving Doping Efficiency of P⁺ Implanted Ions in 4H-SiC
p.393

Simulation of the Incomplete Ionization of the n-Type Dopant Phosphorus in 4H-SiC, Including Screening by Free Carriers
p.397

Effects of Process Variations on Silicon Carbide Devices for Extreme Environments
p.401

Two-Dimensional Modeling of Aluminum-Ion Implantation into 4H-SiC
p.405

DLTS Measurements on 4H-SiC JBS-Diodes with Boron Implanted Local P-N Junctions
p.409

Impact of Surface Morphology on the Electrical Properties of Al/Ti Ohmic Contacts on Al-Implanted 4H-SiC
p.413

Influence of Annealing Parameters on Surface Roughness, Mobility and Contact Resistance of Aluminium Implanted 4H SiC
p.417

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Effects of Process Variations on Silicon Carbide Devices for Extreme Environments

Abstract:

The variation in device process parameters is a core issue in the realisation of complex SiC logic for extreme environments. Factorial design was used to study the effect of variation in four key process parameters on the threshold voltage of an n-channel lateral JFET. Each parameter is simultaneously varied by +/-10% from the default value and the individual and combined effects were calculated at 300, 600 and 1000K. Consequently, we show how these variations in device parameters degrade the threshold voltage, VI, and, hence, the noise margin of logic inverter.