High Quality 3C-SiC Substrate for MOSFET Fabrication

Hiroyuki Nagasawa; Takamitsu Kawahara; Kuniaki Yagi; Naoki Hatta; Hidetsugu Uchida; Motoki Kobayashi; Sergey A. Reshanov; Romain Esteve; Adolf Schöner

doi:10.4028/www.scientific.net/MSF.711.91

Paper Titles

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High Frequency 3C-SiC AFM Cantilever Using Thermal Actuation and Metallic Piezoresistive Detection
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Detailed Experimental Study of Mean and Gradient Stresses in Thin 3C-SiC Films Performed Using Micromachined Cantilevers
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Electrical Characteristics of SiC UV-Photodetector Device from the P-I-N Structure Behaviour to the Junction Barrier Schottky Structure Behaviour
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HomeMaterials Science ForumMaterials Science Forum Vol. 711High Quality 3C-SiC Substrate for MOSFET...

High Quality 3C-SiC Substrate for MOSFET Fabrication

Abstract:

Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm^-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm^-1.

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Materials Science Forum (Volume 711)

Pages:

91-98

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.711.91

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Online since:

January 2012

Authors:

Hiroyuki Nagasawa, Takamitsu Kawahara, Kuniaki Yagi, Naoki Hatta, Hidetsugu Uchida, Motoki Kobayashi, Sergey A. Reshanov, Romain Esteve, Adolf Schöner

Keywords:

3C-SiC, Annihilation, Antiphase Boundary (APB), Blocking Voltage, EBIC, Leakage Current, MOSFET, PEM, P-N Diode, Simulation, Stacking Fault, Termination

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