The Influence of Gate Material, SiO₂ Fabrication Method and Gate Edge Effect on Interface Trap Density in 3C-SiC MOS Capacitors

Abstract:

This paper reports on results of interface trap analysis of 3C-SiC MOS capacitors fabricated using four different gate materials and two SiO₂ oxide preparation methods. The results indicate that post-deposition annealing in wet oxygen of PECVD deposited SiO₂ samples increases the near-interface or slow trap densities, compared with wet oxygen thermally oxidized samples. It has also been found that the energy distribution, D_it, of electron states at the oxide/SiC interface of MOS capacitors with different sizes depend on the factor R=P/A, where P stands for the gate perimeter and A for the gate area, which is related to the amount of stress under the edge of the metallic gate.

• Periodical: Materials Science Forum (Volume 711)
• Pages: 109-113
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.711.109
• Online since: January 2012
• Authors: Tomasz Gutt, Tomasz Malachowski, Henryk M. Przewlocki, Olof Engström, Mietek Bakowski, Romain Esteve
• Keywords: 3C-SiC, C-V, Interface Trap, Mechanical Stress

References

[1] E.W.S. Caetano, E.F. Bezerra, V.N. Freire, J.A.P. da Costa, E.F. da Silva Jr, Ultrafast electron drift velocity overshoot in 3C–SiC, Solid State Communications, 113/9 (2000) 539-542.

DOI: 10.1016/s0038-1098(99)00522-0

[2] V.V. Afanas_ev, F. Ciobanu, G. Pensl, A. Stesmans, in: W.J. Choyke, H. Matsunami, G. Pensl (Eds.), Silicon Carbide Recent Major Results, Springer, Berlin, 2004.

DOI: 10.1007/978-3-642-18870-1

[3] J. Lorenzzi, R. Esteve, N. Jegenyes, S.A. Reshanov, A. Schöner and G. Ferro, MOS Capacitors Fabricated on 3C-SiC(111) Layers Grown pn 6H-SiC(0001), Journ. of the Electrochem. Soc., 158/6 (2011) H630-H634.

DOI: 10.1149/1.3565169

[4] A. Pérez-Tomás, P. Godignon, N. Mestres, R. Pérez, J. Millán, A study of the influence of the annealing processes and interfaces with deposited SiO2 from tetra-ethoxy-silane for reducing the thermal budget in the gate definition of 4H–SiC devices, Thin Solid Films, 513 (2006) 248–252.

DOI: 10.1016/j.tsf.2005.12.308

[5] R. Esteve, S.A. Reshanov, S. Savage, M. Bakowski, W. Kaplan, S. Persson, A. Schöner and C.-M. Zetterling, Toward 4H-SiC MISFETs Devices Based on ONO (SiO2-Si3N4-SiO2) Structures, Journ. of the Electrochem. Soc., 158(5) (2011) H496-H501.

DOI: 10.1149/1.3556119

[6] E.H. Nicollian, J.R. Brews, MOS Physics and Technology, Wiley, New York, 1982.

[7] T. Gutt, H.M. Przewłocki and M. Bakowski, A C-V method of slow-switching interface traps identification in silicon carbide MOS structures, Materials Sci. Forum, 645-648 (2010) 523-526.

DOI: 10.4028/www.scientific.net/msf.645-648.523

[8] T. Gutt, Influence of oxidation rate and post-metallization annealing on distributions of deep interface traps in 4H-n-SiC:SiO2, Proc. MIPRO 2010/MEET&GVS, Opatija, 2010, pp.48-51.

[9] A. Kudla, H.M. Przewlocki, L. Borowicz, D. Brzezinska, W. Rzodkiewicz, Photoelectrical measurements of the local value of the contact potential difference in the metal–insulator semiconductor (MIS) structures, Thin Solid Films, 450/1 (2004) 203-206.

DOI: 10.1016/j.tsf.2003.10.147

[10] H.M. Przewlocki, A. Kudla, K. Piskorski, D. Brzezinska, Distributions of barrier heights, difference of effective contact potential, and local values of flat-band voltage in Al–SiO2–Si and poly–Si–SiO2–Si structures, Thin Solid Films, 516/12 (2008) 4184-4189.

DOI: 10.1016/j.tsf.2007.11.005

[11] C. H. Bjorkman, J. T. Fitch, and G. Lucovsky, Correlation between midgap interface state density and thickness averaged oxide stress and strain at Si/Si02 interfaces formed by thermal oxidation of Si, Appl. Phys. Lett., 56/20 (1990) 1983-1985.

DOI: 10.1063/1.103228

[12] D. Pierreux, A. Stesmans, R.J. Jaccodine, M.-T. Lin, T.J. Delph, Electron spin resonance study of the effect of applied stress during thermal oxidation of (1 1 1)Si on inherent Pb interface defects, Microelectronic Engineering, 72 (2004) 76–80.

DOI: 10.1016/j.mee.2003.12.019

[13] Chia-Nan Lin, Yi-Lin Yang, Wei-Ting Chen, Shang-Chih Lin, Kai-Chieh Chuang, Jenn-Gwo Hwu, Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide, Microelectronic Engineering, 85 (2008) 1915–1919.

DOI: 10.1016/j.mee.2008.06.010

[14] Sang Ho Bae, Seung-Chul Song, KiSik Choi, G. Bersuker, G.A. Brown, Dim-Lee Kwong, Byoung Hun Lee, Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric, Microelectronic Engineering, 83 (2006) 460–462.

DOI: 10.1016/j.mee.2005.11.010

[15] B. Raeissi, J. Piscator, O. Engström, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, H.J. Osten, High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy, Solid-State Electronics, 52 (2008) 1274–1279

DOI: 10.1016/j.sse.2008.04.005

[16] P. Borowicz, T. Gutt, T. Małachowski, M. Latek, Carbonic inclusions on SiC/SiO2 interface investigated with Raman Scattering, Diamond and Related Materials, 20 (2011) 665-674.

DOI: 10.1016/j.diamond.2011.03.019