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Demonstration of SiC Vertical Trench JFET Reliability

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Abstract:

This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

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Silicon Carbide and Related Materials 2011 View Preview

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Periodical:

Materials Science Forum (Volumes 717-720)

Pages:

1017-1020

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.717-720.1017

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Online since:

May 2012

Authors:

Kevin M. Speer, Kiran Chatty, Volodymyr Bondarenko, David C. Sheridan, Kevin Matocha, Jeff B. Casady

Keywords:

Degradation, Dislocation, Junction Field Effect Transistor (JFET), Reliability, Silicon Carbide (SiC), Stacking Fault, Transistor

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© 2012 Trans Tech Publications Ltd. All Rights Reserved

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