Evaluation of SiC Stack Cascode for 200°C Operations

Xue Qing Li; Peter Alexandrov; John Hostetler; Anup Bhalla

doi:10.4028/www.scientific.net/MSF.778-780.879

Paper Titles

The Cryogenic Testing and Characterisation of SiC Diodes
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Comparison of 5kV SiC JBS and PiN Diodes
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650V SiC JFET for High Efficiency Applications
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Gate-Drive Voltage Design for 600-V Vertical-Trench Normally-Off SiC JFETs toward 94% Efficiency Server Power Supply
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Evaluation of SiC Stack Cascode for 200°C Operations
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Beam Acceleration Experiment with SiC Based Power Supply and the Next Generation SiC-JFET Package
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The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study
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Monolithic Integration of Power MESFET for High Temperature SiC Integrated Circuits
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SiC Current Limiting FETs (CLFs) for DC Applications
p.895

HomeMaterials Science ForumMaterials Science Forum Vols. 778-780Evaluation of SiC Stack Cascode for 200°C...

Evaluation of SiC Stack Cascode for 200°C Operations

Abstract:

This paper evaluates the static and dynamic characteristics of a 1.2kV SiC stack-cascode at junction temperatures (T_j) up to 200°C. The experimental results show that, at T_j = 200°C, the SiC stack-cascode can be switched stably under a 600V-17A inductive load condition and can withstand an avalanche current of 13A for 9μs (Eav = 116mJ) for a 1.5mH load inductor. The SiC stack-cascode has no degradation in on-resistance, threshold voltage and blocking characteristics after 80 hours HTRB reliability test at 200°C ambient. These promising experimental results indicate the possibility of the SiC stack-cascode for reliable 200°C operations.

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Periodical:

Materials Science Forum (Volumes 778-780)

Pages:

879-882

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.778-780.879

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Online since:

February 2014

Authors:

Xue Qing Li*, Peter Alexandrov, John Hostetler, Anup Bhalla

Keywords:

Gate Charge, HTRB, SiC JFET, Stack Cascode, Switching Test, UIS Capability

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References

[1] J.W. Palmour, C.H. Carter, C.E. Weitzel, and K.J. Nordquist, Mater. Res. Soc. Symp. Proc., 1994, 339, pp.133-144.

Google Scholar

[2] A. Elasser and T.P. Chow, Proceedings of The IEEE, Vol. 90, No. 6, pp.969-986, (2002).

Google Scholar

[3] F. R. Robin Kelley, and Dan Schwob, Optimized Gate Driver for Enhanced-Mode SiC JFET, Proceeding of PCIM, Nuremberg , Germany (2009).

Google Scholar

[4] S. DasGupta, R.J. Kaplar, M.J. Marinella, M.A. Smith, and S. Atcitty, Reliability Physics Symposium (IRPS), 2012 IEEE International, 15-19 April 2012, pp. 3D. 3. 1-3D. 3. 5.

DOI: 10.1109/irps.2012.6241817

Google Scholar

[5] Datasheets of silicon carbide power MOSFET SCT30N120.

Google Scholar

[6] http: /www. aosmd. com/res/news/news-article-1326744746011/SiC%20Stack%20Cascode_PR. pdf.

Google Scholar

[7] F. Björk, M. Treu, J. Hilsenbeck, M.A. Kutschak, D. Domes, and R. Rupp, Materials Science Forum, Vol. 679 - 680, 2011, pp.587-590.

DOI: 10.4028/www.scientific.net/msf.679-680.587

Google Scholar

[8] R. Siemienieca, G. Nöbauera, and D. Domesb, Stability and performance analysis of a SiC-based cascode switch and an alternative solution, Microelectronics Reliability, Vol. 52, Issue 3, March 2012, p.509–518.

DOI: 10.1016/j.microrel.2011.12.006

Google Scholar