Time Resolved Gate Oxide Stress of 4H-SiC Planar MOSFETs and NMOS Capacitors

Martin Domeij; Benedetto Buono; Krister Gumaelius; Fredrik Allerstam

doi:10.4028/www.scientific.net/MSF.858.611

Paper Titles

Negative Bias Temperature Instability of SiC MOSFET
p.595

Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices
p.599

Quantified Density of Active near Interface Oxide Traps in 4H-SiC MOS Capacitors
p.603

Impact of Al Doping Concentration at Channel Region on Mobility and Threshold Voltage Instability in 4H-SiC Trench N-MOSFETs
p.607

Time Resolved Gate Oxide Stress of 4H-SiC Planar MOSFETs and NMOS Capacitors
p.611

Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors
p.615

Microscopic Difference between Dry and Wet Oxidations of C-Face 4H-SiC MOSFFETs Studied by Electrically Detected Magnetic Resonance
p.619

High Temperature Nitridation of 4H-SiC MOSFETs
p.623

Improvement of SiO₂/4H-SiC Interface Quality by Post-Oxidation Annealing in N₂ at High-Temperatures
p.627

HomeMaterials Science ForumMaterials Science Forum Vol. 858Time Resolved Gate Oxide Stress of 4H-SiC Planar...

Time Resolved Gate Oxide Stress of 4H-SiC Planar MOSFETs and NMOS Capacitors

Abstract:

Lateral SiC MOSFETs and NMOS capacitors were fabricated and electrically evaluated for channel mobility, D_IT and gate oxide breakdown. Time resolved measurements of V_TH and V_FB drift during gate bias stress were performed resulting in logarithmic time dependence for moderate stress time and temperature. Gate bias stress was also carried out during 20 hours at temperatures up to 225 C. Stress times resulting in a V_TH shift of 500 mV were determined and an activation energy E_A=0.86 eV was extracted for the V_TH drift.