Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

Yoshihito Katsu; Takuji Hosoi; Yuichiro Nanen; Tsunenobu Kimoto; Takayoshi Shimura; Heiji Watanabe

doi:10.4028/www.scientific.net/MSF.858.599

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HomeMaterials Science ForumMaterials Science Forum Vol. 858Impact of NO Annealing on Flatband Voltage...

Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

Abstract:

We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (V_FB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the V_FBshift due to hole trapping was found to be suppressed by NO annealing. However, the V_FB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

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Silicon Carbide and Related Materials 2015

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Periodical:

Materials Science Forum (Volume 858)

Pages:

599-602

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.858.599

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Online since:

May 2016

Authors:

Yoshihito Katsu*, Takuji Hosoi, Yuichiro Nanen, Tsunenobu Kimoto, Takayoshi Shimura, Heiji Watanabe

Keywords:

4H-SiC, Flatband Voltage, Hole Traps, MOS, Oxide Nitridation in NO, Post Oxidation Annealing (POA), Threshold Voltage Instability

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