Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers

Kevin Matocha; Sujit Banerjee; Kiran Chatty

doi:10.4028/www.scientific.net/MSF.858.803

Paper Titles

Optimization of 1700V 4H-SiC JBS Diode Parameters
p.782

High-Voltage Ultra-Fast Pulse Diode Stack Based on 4H-SiC
p.786

High Voltage Diffusion-Welded Stacks on the Basis of SiC Schottky Diodes
p.790

Wide Band Gap Semiconductor Technology for Energy Efficiency
p.797

Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers
p.803

Short Circuit Robustness of 1200 V SiC Junction Transistors and Power MOSFETs
p.807

Repetitive Short-Circuit Tests on SiC VMOS Devices
p.812

Comparative Simulation Study of Dynamic Behavior of the Body-Diode for 4H-SiC JFET and MOSFET
p.817

Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs
p.821

HomeMaterials Science ForumMaterials Science Forum Vol. 858Advanced SiC Power MOSFETs Manufactured on 150mm...

Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers

Abstract:

An advanced silicon carbide power MOSFET process was developed and implemented on a high-volume 150mm silicon production line. SiC power MOSFETs fabricated on this 150mm silicon production line were demonstrated with blocking voltage of 1700V with V_GS=0V. These SiC MOSFETs have a specific on-resistance as low as 3.1 mΩ-cm² at room temperature, increasing to 6.7 mΩ-cm² at 175°C. Devices were packaged in TO-247 package and measured to have on-resistance of 45 mΩ with V_GS=20V at room temperature. Clamped inductive switching characterization of these SiC MOSFETs shows turn-off losses as low as 110 uJ (700V, 19.5A). The high-temperature gate bias stability was characterized at positive (+20) and negative gate bias (-10V) at 175°C. After 750 hours of gate stress at a gate bias of V_GS=+20V and 175°C, we observe less than a 250mV shift in the threshold voltage. After 750 hours of stress at V_GS=-10V and 175°C, we characterize a threshold voltage shift less than 100mV. This shows promise for high-volume production of reliable SiC MOSFETs on 150mm wafers.

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Materials Science Forum (Volume 858)

Pages:

803-806

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.858.803

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Online since:

May 2016

Authors:

Kevin Matocha*, Sujit Banerjee, Kiran Chatty

Keywords:

Gate Oxide Reliability, MOSFET, Negative Bias Temperature Instability (NBTI), PBTI, SiC MOSFET, Threshold Voltage Instability

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