Analysis of Interface Trap Density and Channel Mobility in 4H-SiC NMOS Capacitors and Lateral MOSFETs

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Abstract:

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

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115-118

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May 2017

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© 2017 Trans Tech Publications Ltd. All Rights Reserved

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[1] H. Yoshioka, T. Nakamura, T. Kimoto, Journal of Applied Physics. Vol. 111 (2012) 014502.

Google Scholar

[2] H. Yoshioka, J. Sensaki, A. Shimozato, Y. Tanaka, H. Okumura, Applied Physics Letters. Vol. 104 (2014) 083516.

Google Scholar

[3] J. Senzaki, K. Kojima, S. Harada, R. Kosugi, S. Suzuki, T. Suzuki, K. Fukuda, IEEE Electron Device Letters. Vol. 23 (2002) 13.

DOI: 10.1109/55.974797

Google Scholar

[4] M. Domeij, B. Buono, K. Gumaelius, F. Allerstam, Materials Science For. Vol. 858 (2016) 611.

Google Scholar

[5] J. A. Cooper, Phys. Status Solidi A, Vol. 92 (1997) 305.

Google Scholar

[6] S. Dhar, S-H. Ryu, A. K. Agarwal, , IEEE Transactions on Electron Devices. Vol. 57 (2010) 1195.

Google Scholar