Subthreshold Drain Current Hysteresis of Planar SiC MOSFETs

Besar Asllani; Alberto Castellazzi; Dominique Planson; Hervé Morel

doi:10.4028/www.scientific.net/MSF.963.184

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HomeMaterials Science ForumMaterials Science Forum Vol. 963Subthreshold Drain Current Hysteresis of Planar...

Subthreshold Drain Current Hysteresis of Planar SiC MOSFETs

Abstract:

V_TH instabilities of SiC MOSFET are made of a permanent and a recoverable part. V_TH hysteresis is a recoverable instability which affects the operation of the device since the threshold voltage depends on the negative bias applied previously. In this paper, the phenomenon is assessed through experiments and TCAD simulation. The results are in good agreement and show that the V_TH hysteresis is mainly caused by the hole trapping in the oxide near the interface. The C(V) characteristics of the measured device is similar to the simulated device having a concentration of 10¹² holes/cm² trapped at the interface.

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Periodical:

Materials Science Forum (Volume 963)

Pages:

184-188

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.963.184

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Online since:

July 2019

Authors:

Besar Asllani*, Alberto Castellazzi, Dominique Planson, Hervé Morel

Keywords:

Gate Oxide, MOSFET Reliability, Oxide Traps, SiC-MOSFET, TCAD Simulation, V_TH Instability

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