Surface Preparation and Passivation of III-V Substrates for Future Ultra-High Speed, Low Power Logic Applications

Abstract:

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III-V compound semiconductors have been recognized among the potential options for continuing transistor power-performance scaling owing to their ultra high charge carrier mobility. In order to realize their potential in high performance and lower-power digital logic applications, there must be strong gate control and a high Ion-Ioff ratio, achieved by integrating a stable, ultra thin high-K dielectric between the semiconductor and the gate [1, 2]. Unlike Si, which has long benefited from its very stable native oxide, III-V materials suffer from their poor native oxides that cause charge traps and Fermi level pinning at the semiconductor-oxide interface. Attempts to deposit high-K directly on III-V often produce MIS structures with fast surface state and CV instability [3].

Info:

Periodical:

Solid State Phenomena (Volumes 145-146)

Edited by:

Paul Mertens, Marc Meuris and Marc Heyns

Pages:

165-167

DOI:

10.4028/www.scientific.net/SSP.145-146.165

Citation:

W. Rachmady et al., "Surface Preparation and Passivation of III-V Substrates for Future Ultra-High Speed, Low Power Logic Applications", Solid State Phenomena, Vols. 145-146, pp. 165-167, 2009

Online since:

January 2009

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Price:

$35.00

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