Application of Single-Wafer Wet Cleaning Prior to Epitaxial SiGe Process

Kenichi Sano; Masayuki Wada; Frederik E. Leys; Roger Loo; Andriy Hikavyy; Paul W. Mertens; James Snow; Akira Izumi; Katsuhiko Miya; Atsuro Eitoku

doi:10.4028/www.scientific.net/SSP.145-146.173

Paper Titles

Single Wafer Ozone-Based Processing for Effective Edge Fluoropolymer Cleaning
p.155

Cleanliness Management in Advanced Microelectronic
p.159

Surface Preparation and Passivation of III-V Substrates for Future Ultra-High Speed, Low Power Logic Applications
p.165

Preparation and Characterization of Self-Assembled Monolayers on Germanium Surfaces
p.169

Application of Single-Wafer Wet Cleaning Prior to Epitaxial SiGe Process
p.173

Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination
p.177

Silicon Surface Preparation and Passivation by Vapor Phase of Heavy Water
p.181

Defects of Silicon Substrates Caused by Electro-Static Discharge in Single Wafer Cleaning Process
p.185

Three-Step Room Temperature Wet Cleaning Process for Silicon Substrate
p.189

HomeSolid State PhenomenaSolid State Phenomena Vols. 145-146Application of Single-Wafer Wet Cleaning Prior to...

Application of Single-Wafer Wet Cleaning Prior to Epitaxial SiGe Process

Abstract:

Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].